SK hynix broke new technological ground to achieve the recent landmark development of the world’s first DDR5¹ product built using the 1c² node. Boasting improved operating speed and power efficiency compared to the previous generation, the 16 gigabit (Gb) 1c DDR5 represents a monumental leap forward in DRAM process technology.

¹Double Data Rate 5 (DDR5): A server DRAM that effectively handles the increasing demands of larger and more complex data workloads by offering enhanced bandwidth and power efficiency compared to the previous generation, DDR4.
²1c: The sixth generation of the 10 nm DRAM process technology, which was developed in the order of 1x-1y-1z-1a-1b-1c.

The groundbreaking achievement is just the latest in a long line of breakthroughs by the company to advance its DDR5 lineup. This remarkable progress is not only a testament to SK hynix’s technological prowess but also to its innovative approach to the validation process.

This episode of Rulebreakers’ Revolutions will focus on how the company’s differentiated validation strategy is enabling it to navigate the challenges posed by a diversifying server CPU market, contributing to SK hynix’s DRAM leadership including its cutting-edge DDR5 server DRAM.

The Mission: Strengthening Validation in an Increasingly Diverse CPU Market

SK hynix has faced various challenges throughout the successful development of its latest 1bnm and 1cnm DDR5 products. As each generation of DDR5 is based on a new DRAM process technology, a rigorous validation process is required to ensure the products’ performance and reliability as well as their compatibility with customer systems. This means that the company has had to continually adapt and strengthen its approach to validation for next-generation technologies.

In addition to validating new technologies, SK hynix also had to respond to the growing diversity of server CPU suppliers in the market. Traditionally, Intel has dominated the sector which has resulted in semiconductor companies primarily focusing their efforts on validating their products with the U.S. tech giant. However, while Intel still leads the sector, AMD and Arm-based suppliers are gradually increasing their market share, especially in cloud and specialized workloads, creating a more fragmented server CPU landscape.

Amid these shifting market dynamics, SK hynix is required to ensure its DDR5 products’ compatibility and reliability across a broader range of server CPU architectures. This is because CPU companies integrate their chips into a wide range of hardware, placing greater pressure to ensure compatibility with various server CPU types, which is essential for DDR5’s widespread adoption. In particular, early alignment with customers during the product planning stage is increasingly important to meet the needs of various companies and handle numerous server CPU types.

Faced with the challenge of validating new technologies in a diversifying server CPU market, SK hynix is consistently refining its validation methods to ultimately solidify its leadership in the server DRAM field.

SK hynix employs a differentiated validation approach to ensure DDR5’s comparability with various server CPUs

Compatibility, Collaboration, & Customized Testing: Three Cs Key to Optimized Validation

Although SK hynix had an established validation procedure for its products, the company has adjusted its process for the latest DDR5 products. Typically, validation begins in the pre-development stage by verifying that the design meets the specifications required by server customers and adheres to JEDEC³ standards. The company then prepares memory validation samples in collaboration with external partners and aligns the test environment with SoC⁴ companies, which play a key role in validation. While CPU companies are the customers for DDR5, SoC companies provide reputable third-party validation to verify the product’s readiness for real-world system application. Continuing with the validation process, the next stage involves internal testing to identify and resolve any defects. The samples are then sent to SoC companies for further tests to complete the process.

³JEDEC Solid State Technology Association: With over 350 member companies, JEDEC is the global leader in developing open standards for the microelectronics industry.
⁴System-on-chip (Soc): An integrated circuit that combines all the components of an electronic device onto a single chip.

For its recent DDR5 products, however, the company is taking a rulebreaking approach to validation that sets it apart from the rest of the field. This unique method is highlighted in the ongoing validation process for the 1bnm and 1cnm DDR5, which features several differentiated strategies.

For example, to ensure compatibility with a wide range of server CPUs, SK hynix is conducting validation on a wide range of systems—even those that have yet to be released. This involves close collaboration with SoC companies to discuss required technologies and perform co-validation, ensuring that potential issues with samples are addressed early in the development process.

As well as working with external SoC companies, SK hynix is also conducting improved internal collaboration throughout the validation process to enhance the completeness of the 1c DDR5. Departments responsible for process, design, and testing are closely working together to ensure the cost efficiency of test infrastructure and optimize the sample management and testing process. Moreover, the departments are identifying and improving potential defects in advance through rigorous simulation and aging tests, thereby securing the product’s reliability and stability.

Another key step in the validation process involves the development of customer-specific tests based on tailored validation scenarios. Recognizing that each customer has different requirements and various products, SK hynix evaluates and verifies various scenarios at the scale and volume testing stages. By predicting potential defects under actual usage conditions, the company aims to ensure that the 1c DDR5 performs reliably across a wide range of applications and platforms.

SK hynix’s validation strategy involves ensuring broad compatibility, internal collaboration, and customized testing

Validation: The Final Piece of the DDR5 Evolution Puzzle

Since SK hynix launched the world’s first DDR5 DRAM in 2020, rapid and reliable validation has played a crucial role in the company’s outstanding progress in the field. The company’s numerous milestones in DDR5 and DRAM scaling technology include the industry-first validation of its 1anm DDR5 with the 4th Gen Intel® Xeon® Scalable processor in January 2023. In May of the same year, the company announced it had developed the industry’s most advanced 1bnm DDR5 and begun validation with Intel.

While the semiconductor industry has faced increasing difficulty in advancing the 10 nm process technology, SK hynix overcame the obstacles thanks in part to its robust validation strategy. This is set to continue with the validation of its 1c DDR5 product, which aims to verify key specifications of the new DRAM.

The 1c DDR5 offers superior operating speeds and power efficiency compared to the previous generation

In comparison to 1b DDR5, the 1c DDR5 product offers 11% faster operating speeds of 8 gigabits (Gbps) per second and a more than 9% improvement in power efficiency. As part of the validation process which is progressing smoothly, SK hynix is currently working with server CPU suppliers to verify the product’s stable performance and ensure it meets the expected operational standards.

Looking ahead, the successful development of 1c DDR5 has established a benchmark for subsequent DRAM product lines to be developed with the 1c node, including HBM⁵, LPDDR⁶, and GDDR⁷. In terms of validation, the company is striving to enhance the efficiency and overall process for future products. In particular, the company aims to reduce risk factors in future validation processes, ensuring higher quality and reliability for its next-generation products.

⁵High Bandwidth Memory (HBM): A high-value, high-performance product that possesses much higher data processing speeds compared to existing DRAMs by vertically connecting multiple DRAMs with through-silicon via (TSV).
⁶Low Power Double Data Rate (LPDDR): A line of low-power DRAM for mobile devices, including smartphones and tablets, aimed at minimizing power consumption and featuring low voltage operation.
⁷Graphics DDR (GDDR): A standard specification of graphics DRAM defined by the Joint Electron Device Engineering Council (JEDEC) and specialized for processing graphics more quickly. It is now one of the most popular memory chips for AI and big data applications.

Rulebreaker Interview: Yoosung Lee, DRAM Server Product Planning

To find out more about the company’s innovative approach to validation, the SK hynix Newsroom spoke with Technical Leader (TL) Yoosung Lee of DRAM Server Product Planning. Lee’s department plays a key role in collaborating with customers such as SoC companies to validate products. He discussed how the company encourages employees to take a different approach to their work and the improvement plans for validation.

<Other articles from this series>

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

The post [Rulebreakers’ Revolutions] How SK hynix’s Server DRAM Validation Process Succeeds in a Diverse Server CPU Market first appeared on SK hynix Newsroom.

¹1c: The sixth generation of the 10 nm DRAM process technology, which was developed in the order of 1x-1y-1z-1a-1b-1c.
²High Bandwidth Memory (HBM): A high-value, high-performance product that possesses much higher data processing speeds compared to existing DRAMs by vertically connecting multiple DRAMs with through-silicon via (TSV).

To find out more about SK hynix’s technological capabilities and DRAM roadmap as well as the development of 1c technology, the newsroom held a roundtable with key project members of the 1c DDR5. Six vice presidents from the company took part in the discussion: Taekyoung Oh of the 1c Technology Taskforce (1c Tech TF); Joohwan Cho of DRAM Design; Youngmann Cho of DRAM Process Integration (DRAM PI); Changkyo Jung of DRAM Product Engineering (DRAM PE); Sooyong Son of Development Test; and Hyungsoo Kim of DRAM Application Engineering (DRAM AE), who led the development of the 1c technology.

From left: Hyungsoo Kim (DRAM AE), Youngmann Cho (DRAM PI), Taekyoung Oh (1c Tech TF), Joohwan Cho (DRAM Design), Changkyo Jung (DRAM PE), and Sooyong Son (Development Test)

Journey to 1c: A Technological Breakthrough Achieved Through Collective Efforts

The 1c technology is an ultra-fine memory fabrication process in the low 10 nm range. Built using the 1c node, the 16 Gb DDR5 reaches an operating speed of 8 gigabits (Gbps) per second, an 11% increase over the previous generation—1b DDR5—and offers more than a 9% improvement in power efficiency. In addition to achieving performance gains, SK hynix developed new materials for the EUV lithography³ process and maximized efficiency through design innovations, resulting in both process optimization and cost reductions.

³Extreme ultraviolet (EUV) lithography: A semiconductor manufacturing technique that uses extreme ultraviolet light to create intricate patterns on silicon wafers.

To achieve these advancements and ultimately develop 1c technology, SK hynix had to overcome numerous technical challenges. This roundtable highlights the contributions of each department to achieve this feat, lifting the lid on how the engineering team secured the coveted “world’s first” title.

From left: Hyungsoo Kim, Taekyoung Oh, and Youngmann Cho discuss the company’s approach to developing 1c technology

Taekyoung Oh (1c Tech TF): “The primary goal of the 1c Tech TF, which led to the development of 1c technology, was to be the ‘first to develop.’ To achieve this, we chose a strategy that expanded upon the already proven 1b platform. We also streamlined the traditional three-stage development process—testing, design, and mass-production readiness—into a two-stage process, focusing only on design and mass-production readiness. For complex technical elements, such as the capacitor module, we integrated their development directly into the mass production process. As a result, we reduced the development time of 1c technology by two months compared to the previous generation.”

Joohwan Cho (DRAM Design): “Leveraging our experience with the proven 1b technology reduced technical risks, but the smaller cell size and increased resistance still posed significant challenges. To tackle these issues, we introduced several design innovations, including higher circuit density and enhanced sensing performance, which boosted data processing speeds and reduced power consumption. Additionally, through close collaboration with the manufacturing side, we maximized the number of net dies⁴ to improve cost competitiveness.”

Youngmann Cho (DRAM PI): “Our approach of expanding the 1b platform proved to be effective in reducing trial and error during the process refinement of 1c technology. Leveraging our experience with 1b, we were able to predict and resolve potential issues in 1c technology in advance. In particular, by identifying and addressing quality risks early on such as transistor degradation⁵ as well as applying new materials, we were able to secure the reliability of the miniaturized devices.”

⁴Net die: The number of viable chips (die) that can be produced from a single wafer during the semiconductor manufacturing process.
⁵Degradation: The deterioration of an insulator’s chemical and physical properties caused by external or internal factors.

From left: Changkyo Jung, Sooyong Son, and Joohwan Cho talk about overcoming challenges during the development process

Changkyo Jung (DRAM PE): “When developing new technology, it’s inevitable to encounter new problems that previously didn’t exist. As processes become more miniaturized, different characteristics become increasingly critical, leading to potential issues such as yield loss. For 1c technology, we utilized trimming⁶ techniques to enhance key performance levels, securing both yield and quality.”

⁶Trimming: A technique that boosts performance by utilizing electronic fuses (eFuse) without requiring changes to the semiconductor design.

Sooyong Son (Development Test): “For our department, a major challenge was reducing the test duration for 1c DDR5 products to meet the development timeline. In particular, we conducted development almost simultaneously with other key products, so we needed to improve the testing efficiency. To address this, we expanded our testing infrastructure and strategically deployed implementation systems, allowing us to complete the testing process ahead of schedule.”

Hyungsoo Kim (DRAM AE): “From our point of view, the biggest technical challenge was validating the ultra-high-speed and high-performance characteristics of the 1c DDR5. To ensure the system-level functionality of the product, which achieved the industry’s highest speed, we developed our own verification infrastructure capable of operating at 8 Gbps for the first time. Additionally, we independently developed software that could both verify and predict potential defects, securing the company a unique competitive edge.”

The Power of ‘One Team’: Establishing Unparalleled Technological Leadership

What is the driving force behind SK hynix’s ability to demonstrate unparalleled technological leadership in the DRAM market? All the participants in the roundtable unanimously emphasized “systematic collaboration” and SK hynix’s “one team” spirit.

Taekyoung Oh singles out collaboration as the key to successfully developing 1c technology

Taekyoung Oh (1c Tech TF): “I believe SK hynix’s technology development capabilities are improving through innovations across multiple areas. These innovations include enhancements in work methods such as taskforce operations, platform-based development, and early mass production fab operation strategies. Above all, I think it is the ‘one team’ spirit of the members that has driven all the achievements. The implementation of the two-stage development process, the development of new materials to improve EUV patterning performance, and cost reduction would not have been possible without a solid foundation of collaboration.”

Changkyo Jung says the company’s “one team” spirit helped to quickly identify and resolve issues

Changkyo Jung (DRAM PE): “The most important factor in the development process of 1c technology was the ‘one team’ culture. To overcome the many technical challenges that come with being the ‘first’, close collaboration between teams allowed us to identify and resolve issues early on in the process. In particular, seamless collaboration with the design and process departments was crucial for the DRAM PE department in optimizing the screening process.”

Hyungsoo Kim claims close customer communication is vital for DRAM development

Hyungsoo Kim (DRAM AE): “As microfabrication processes become more complex, a multitude of technical challenges emerge. However, I believe the company’s strength to overcome these difficulties ultimately comes from our ‘one team’ spirit, with multiple related teams working toward the same goal.

“Along with a strong internal collaboration, cooperation with customers is also crucial. DRAM is a product that operates within the customer’s system, so their perspective must be considered throughout the entire development process—from product planning to the design, process, testing, and validation stages. It is essential to conduct continuous communication and technical cooperation with customers to achieve our goals.”

Beyond 1c: Maintaining Leadership in Next-Gen DRAM Technology

The greatest significance of 1c technology’s development is that it will be applied across all of SK hynix’s next-generation DRAM product lines, including HBM, LPDDR⁷, and GDDR⁸. What innovations will 1c technology drive, and how will SK hynix’s DRAM evolve moving forward?

⁷Low Power Double Data Rate 5 Turbo (LPDDR5T): Low-power DRAM for mobile devices, including smartphones and tablets, aimed at minimizing power consumption and featuring low voltage operation. LPDDR5T is an upgraded product of the 7th generation LPDDR5X and will be succeeded by the 8th generation LPDDR6.
⁸Graphics DDR (GDDR): A standard specification of graphics DRAM defined by the Joint Electron Device Engineering Council (JEDEC) and specialized for processing graphics more quickly. It is now one of the most popular memory chips for AI and big data applications.

Sooyong Son says that 1c DDR5 is only the beginning of the company’s 1C DRAM lineup

Sooyong Son (Development Test): “The successful development of 1c has demonstrated SK hynix’s superior technological edge, but 1c DDR5 is only the beginning. Going forward, we expect that 1c technology will be integrated into a wide range of DRAM products, driving sustainable growth and innovation while fully meeting the diverse needs of our customers.”

Youngmann Cho states that innovation will help SK hynix overcome DRAM scaling challenges

Youngmann Cho (DRAM PI): “Miniaturization is set to continue as DRAM technology advances beyond 1c. Especially when transitioning to sub-10 nm nodes, there are expected to be limitations in current methods. Overcoming these challenges will require not only maximizing material and equipment performance, but also innovations such as shifting from 2D to 3D cell structures and adopting heterogeneous integration. To address this, SK hynix is continuously enhancing its DRAM development system.”

Joohwan Cho claims preparation is crucial for maintaining DRAM leadership

Joohwan Cho (DRAM Design): “For the company to maintain DRAM technology leadership, we must proactively prepare core technologies in advance based on a long-term technology roadmap. On the design side, we are advancing our systems to accurately predict risks associated with next-generation microfabrication processes, reducing the burden on our teams and strengthening the company’s competitiveness.”

SK hynix plans to finish preparations for the mass production of the 1c DDR5 product within 2024 and begin full-scale market supply from 2025. The 1c technology, which delivers both exceptional performance and cost competitiveness, is expected to further strengthen the company’s leadership. To conclude, the roundtable participants shared their reflections and aspirations as pioneers of the new DRAM paradigm.

The project members plan to build on their success by developing next-gen products in the future

Taekyoung Oh (1c Tech TF): “Being the first to develop 1c technology is not the finish line. We plan to continue to address any gaps and enhance mass production yield and cost competitiveness, thereby ensuring that SK hynix maintains its leadership position.”

Joohwan Cho (DRAM Design): “SK hynix has solidified its position as a true leader in DDR5 development. Building on the success of 1c technology, we will continue to enhance our competitiveness to deliver innovative products in 1d and future generations.”

Youngmann Cho (DRAM PI): “As demand for AI memory surges, customer expectations for high-performance memory are rising as well. The successful development of 1c DDR5 is a highly encouraging milestone. Building on this success, we will continue working to position SK hynix’s DDR5 at the forefront of the high-performance AI memory market.”

Changkyo Jung (DRAM PE): “I’m happy and proud that SK hynix has proven its world-class technology leadership through its timely delivery of products needed by the market, strengthening customer trust. Moving forward, we will continue to solve yield and quality challenges to launch even more refined products.”

Sooyong Son (Development Test): “This achievement is the result of long-term efforts. Building on the SKMS⁹, we will continue working with our team to drive growth and development through an excellent corporate culture and ‘one team’ collaboration.”

⁹SK Management System (SKMS): SK Group’s business management system comprised of SK’s management philosophy and the methodology to implement this approach into actual management.

Hyungsoo Kim (DRAM AE): “SK hynix’s 1c DDR5 will set the standard for high-performance server systems and will lead the market with its outstanding technological prowess. This achievement reflects the efforts and dedication of all the team members involved in the project. We will continue to work together to uphold our ‘world’s best’ title.”

The post Roundtable on World’s First 1c DDR5: How SK hynix Opened a New Paradigm of DRAM Technology first appeared on SK hynix Newsroom.

¹Open Innovation Platform (OIP): A comprehensive design technology infrastructure encompassing all areas of integrated circuit implementation which aims to promote innovation. Members include a variety of semiconductor design and manufacturing companies.
²High Bandwidth Memory (HBM): A high-value, high-performance product that revolutionizes data processing speeds by connecting multiple DRAM chips with through-silicon via (TSV).

SK hynix’s booth at the TSMC OIP Ecosystem Forum 2024

Innovation in Focus: Leading HBM, AI & Data Center Products at the Booth

Situated next to the main TSMC booth, the SK hynix booth featured two main sections which showcased the company’s global No. 1 HBM and AI/data center solutions, respectively.

The HBM section featured the company’s industry-leading HBM3E. Boasting rapid processing speeds, high capacity, and outstanding heat dissipation, HBM3E is optimized for AI applications. This section not only highlighted the technological achievements of SK hynix, but also illustrated the strategic importance of its collaboration with TSMC to push the boundaries of AI innovation. Moreover, SK hynix’s HBM leadership was further underlined by the company’s recent announcement that it had become the first in the industry to begin volume production of the 12-layer HBM3E.

In the AI and data center solutions section, SK hynix presented the industry’s first 16Gb DDR5 product built using the 1c node, the sixth generation of the 10 nm process. Compared to the previous generation, the new product offers 11% faster operating speeds of 8 gigabits per second (Gbps) and 9% greater power efficiency to help data centers cut electricity costs. Marking a significant advancement in DRAM scaling, the 1cnm technology is set to be applied to other SK hynix products in the future.

This section also featured other key products in SK hynix’s portfolio, including DDR5 MCR DIMM³, DDR5 3DS RDIMM⁴, LPCAMM2⁵, GDDR7⁶, and LPDDR5T⁷. Each solution reflects significant advancements in AI memory technology, catering to diverse needs from high-performance computing (HPC) to mobile and graphics-intensive applications.

³Multiplexer Combined Ranks Dual In-line Memory Module (MCR DIMM): A module product with multiple DRAMs bonded to a motherboard in which two ranks—basic information processing units—operate simultaneously, resulting in improved speed.
⁴3D Stacked Memory Registered Dual In-line Memory Module (3DS RDIMM): A high-density memory module used in servers and other applications to vertically connect DRAM dies through TSV, reducing module package height and boosting data transfer speeds.
⁵Low Power Compression Attached Memory Module 2 (LPCAMM2): LPDDR5X-based module solution that offers power efficiency and high performance as well as space savings. It offers performance levels equivalent to two DDR5 SODIMMs, making it optimized for on-device AI.
⁶Graphics DDR (GDDR): A standard specification of graphics DRAM defined by the Joint Electron Device Engineering Council (JEDEC) and specialized for processing graphics more quickly. It is now one of the most popular memory chips for AI and big data applications.
⁷Low Power Double Data Rate 5 Turbo (LPDDR5T): Low-power DRAM for mobile devices, including smartphones and tablets, aimed at minimizing power consumption and featuring low voltage operation. LPDDR5T is an upgraded product of the 7th generation LPDDR5X and will be succeeded by the 8th generation LPDDR6.

Other products on display included DDR5 MCR DIMM, DDR5 3DS RDIMM, LPCAMM2, LPDDR5T, and GDDR7

Presentation on 2.5D SiP Study for Enhancing HBM Quality & Reliability

During the forum, SK hynix’s Byoungdo Lee, Technical Leader of HBM PKG TE, gave a talk titled “A Collaborative Study on 2.5D System-in-Packages for Better Quality and Reliability of HBM.” Having encountered limitations using a proxy package to accurately recreate SiP⁸ conditions for the study, SK hynix opted to conduct open collaboration with companies including TSMC. This collaboration included preliminary evaluations as well as thermal and mechanical simulations at the SiP level. The study found that HBM products with SK hynix’s MR-MUF⁹ technology offer greater quality and reliability, and are ultimately able to overcome stacking limitations.

Additionally, the presentation covered three main advancements for HBM4, the upcoming sixth generation of HBM. Lee addressed the use of base logic die wafers¹⁰ to improve performance and power efficiency, as well as the development of 16-layer HBM utilizing Advanced MR-MUF or hybrid bonding¹¹ packaging technology to meet demand for higher density products. Lastly, Lee spoke about planned SiP-level verification developments which aim to mitigate risks associated with the increased total product thickness.

⁸System-in-Package (SiP): A method of stacking and connecting multiple semiconductor chips in a single package to improve performance and efficiency, enabling advanced functions like high-speed data processing.
⁹Mass reflow-molded underfill (MR-MUF): A technology that ensures secure and reliable connections in densely stacked chip assemblies by melting the bumps between stacked chips.
¹⁰Base logic die wafer: A foundational semiconductor layer that contains the memory controller and logic circuitry, enabling high-speed communication between the stacked memory dies and the system.
¹¹Hybrid bonding: A technology that stacks two or more chips atop one another in the same package, enabling high-density interconnections crucial for advanced HBM products.

SK hynix’s Byoungdo Lee presenting an OIP Partner Technical Talk on enhancing HBM

Strengthening AI Memory Leadership & Strategic Partnerships

At the TSMC OIP Ecosystem Forum 2024, SK hynix underlined its AI memory leadership and strengthened key industry partnerships. By showcasing key products such as the industry-leading HBM3E and the world’s first 1cnm DDR5 product, the company emphasized its ability to break technological boundaries. Looking ahead, the company is set to continue advancing its portfolio through collaboration with global partners to meet the growing needs of the AI era.

The post SK hynix Spotlights AI Memory Solutions & Industry Collaboration at TSMC OIP Ecosystem Forum 2024 first appeared on SK hynix Newsroom.

• 1c node, 6th generation of 10nm process, developed in most efficient way by applying platform of industry-leading 1b technology
• Cost competitiveness improved with adoption of new material, optimization of EUV process, while power efficiency enhanced to help reduce electricity cost of data centers by 30% maximum
• Mass production expected to be ready this year for volume shipment in 2025
• Application of 1c node to leading-edge DRAM products to bring differentiated values to customers

Seoul, August 29, 2024

SK hynix Inc. (or “the company”, www.skhynix.com) announced today that it has developed the industry’s first 16Gb DDR5 built using its 1c node, the sixth generation of the 10nm process.

The success marks the beginning of the extreme scaling to the level closer to 10nm in the memory process technology.

The degree of difficulty to advance the shrinking process of the 10nm-range DRAM technology has grown over generations, but SK hynix has become the first in the industry to overcome the technological limitations by raising the level of completion in design, thanks to its industry-leading technology of the 1b, the fifth generation of the 10nm process.

SK hynix said it will be ready for mass production of the 1c DDR5 within the year to start volume shipment next year.

In order to reduce potential errors stemming from the procedure of advancing the process and transfer the advantage of the 1b, which is widely applauded for its best performing DRAM, in the most efficient way, the company extended the platform of the 1b DRAM for development of 1c.

The new product comes with an improvement in cost competitiveness, compared with the previous generation, by adopting a new material in certain process of the extreme ultra violet, or EUV, while optimizing the EUV application process of total. SK hynix also enhanced productivity by more than 30% through technological innovation in design.

The operating speed of the 1c DDR5, expected to be adopted for high-performance data centers, is improved by 11% from the previous generation, to 8Gbps. With power efficiency also improved by more than 9%, SK hynix expects adoption of 1c DRAM to help data centers reduce the electricity cost by as much as 30% at a time when advancement of AI era is leading to an increase in power consumption.

“We are committed to providing differentiated values to customers by applying the 1c technology equipped with the best performance and cost competitiveness to our major next-generation products including HBM¹, LPDDR6², and GDDR7³,” said Head of DRAM Development Kim Jonghwan. “We will continue to work towards maintaining the leadership in the DRAM space and position as the most-trusted AI memory solution provider.”

¹HBM(High Bandwidth Memory): a high-value, high-performance memory that vertically interconnects multiple DRAM chips and dramatically increases data processing speed in comparison to conventional DRAM products. Since the introduction of the first HBM, the generation has shifted to HBM2, HBM2E, HBM3, HBM3E, HBM4 and HBM4E.
²LPDDR: low power DRAM for mobile devices, including smartphones and tablets, which aims to minimize power consumption and features low voltage operation. The latest specifications are for the 7th generation, succeeding the series that end with 1, 2, 3, 4, 4X, 5 and 5X.
³GDDR(Graphics DDR): a standard specification of graphics DRAM defined by the Joint Electron Device Engineering Council (JEDEC) and specialized for processing graphics more quickly. Its generation has shifted from GDDR3, GDDR5, GDDR5X, GDDR6 to GDDR7. With the newer generation promising faster speed and higher power efficiency, GDDR has now become one of the most popular memory chips for AI.

About SK hynix Inc.

SK hynix Inc., headquartered in Korea, is the world’s top tier semiconductor supplier offering Dynamic Random Access Memory chips (“DRAM”), flash memory chips (“NAND flash”) and CMOS Image Sensors (“CIS”) for a wide range of distinguished customers globally. The Company’s shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxembourg Stock Exchange. Further information about SK hynix is available at www.skhynix.com, news.skhynix.com.

Media Contact

SK hynix Inc.
Global Public Relations

Technical Leader
Kanga Kong
E-Mail: global_newsroom@skhynix.com

Technical Leader
Sooyeon Lee
E-Mail: global_newsroom@skhynix.com

The post SK hynix Develops Industry’s First 1c DDR5 first appeared on SK hynix Newsroom.