Overview of Assembling Conventional Packages

Figure 1 shows the assembly process for plastic packages, which are a type of conventional package. Plastic packages are categorized into leadframe and substrate packages. The first half of the packaging process for these two packages is the same, but the second half differs in how the connection pins are applied.

▲ Figure 1. The steps of assembling leadframe and substrate packages (Source: Hanol Publishing)

Once the wafers are tested, they first go through backgrinding to become the desired thickness. Wafer sawing then follows so the wafers can be cut into chips. Afterwards, chips that are deemed to be of good quality are selected and attached to the leadframe or substrate through the die attach process. The chips are then electrically connected to the substrate through wire bonding before they are sealed with an epoxy molding compound (EMC) for protection. Both leadframe and substrate packages share these steps.

In the next stage, leadframe packages undergo several processes: trimming¹ that separates the leads, solder plating that applies solders to the ends of the leads, and, lastly, forming. The process of forming separates the packages into single units and bends the leads so they can be attached to the system board. As for substrate packages, they are molded before going through solder ball mounting where solder balls are attached to the substrate pads. This is followed by a process of cutting and forming individual packages called singulation. In the following section, the process of assembling conventional packages with an emphasis on the eight steps of producing substrate packages will be explained.

¹ Trimming: A process applied to leadframe packages that removes the dambar, which connects the space between the leads, using a cutting punch.

Step One: Backgrinding

The backgrinding process ensures a wafer is processed with the optimal thickness for its package’s characteristics. This includes processing the wafer’s back and mounting it to a ring frame, as shown in Figure 2.

▲ Figure 2. The four steps of the wafer backgrinding process (Source: Hanol Publishing)

Before grinding the backside of the wafer, a protective tape known as a backgrinding tape is laminated onto the wafer’s front. This is to prevent physical damage to the frontside where the circuit was formed. Next, grinding wheels are applied to the backside of the wafer to make it thinner. A rough grinding wheel is first used at high speed to remove most of the excess material before a fine grinding wheel grinds more delicately and accurately to reach the wafer’s target thickness. Afterwards, a fine pad is used for polishing to smooth the wafer’s surface. If the wafer’s surface is rough, cracks are more likely to occur when stress is applied during subsequent processes and result in the chip breaking. Therefore, it is crucial to reduce the chances of chip breakage by polishing that prevents the formation of cracks.

For packages consisting of a single chip, the wafer is generally grinded to a thickness of about 200 to 250 micrometers (μm). As for stacked packages, the chips—and essentially the wafers as well—need to be even thinner as multiple chips are stacked on the package. However, the residual stress from grinding the wafer’s backside causes shrinkage on the frontside and can potentially bend the wafer into the shape of a smile. Furthermore, the degree of bending becomes more severe as the wafer is thinned. To flatten out the wafer, mounting tape is first applied to the backside of the wafer and then it is attached to the ring frame. The backgrinding tape that was applied to protect the devices on the wafer’s front is then removed again, exposing the semiconductor devices to complete the backgrinding process.

Step Two: Wafer Sawing/Dicing

Wafer sawing is the process of cutting along the scribe lanes² of a wafer in order to break it into chips or dies. Also referred to as the dicing process, wafer sawing is a necessary procedure of the packaging process for chips or dies.

Figure 3 shows an example of a wafer being broken into chips through blade dicing, a method of wafer sawing that uses a wheel-shaped saw blade to cut and separate wafers. This saw blade with a wheel tip strengthened through diamond grit cuts along the wafer’s scribe lanes—the lattice-shaped lines of the wafer on the left of the figure. As the saw blade creates a working tolerance³ when it rotates, the scribe lane must be thicker than the wheel.

² Scribe lane: A space of sufficient width designated for cutting a chip or die from a wafer without affecting nearby devices while allowing for the distribution of the cut pieces.

³ Tolerance: The range of errors in space or values created from the difference of work capabilities.

▲ Figure 3. Sawing a wafer into chips through the blade dicing process (Source: Hanol Publishing)

One issue of blade dicing is that, as the blade physically contacts the wafers during the process, the wafers are more prone to breaking when they are requested to be made thinner. Laser dicing, another method of wafer sawing, resolves a lot of these issues as nothing physically contacts the wafer during the cutting process. Instead, a laser is shot from the back of the wafer during the dicing. Consequently, it is suitable for cutting thin wafers, while the chip remains robust due to the minimal damage to the wafer’s surface.

As wafers have become thinner, there have been proposals to use dicing before grinding (DBG) which reverses the sequence of processes to reduce chip damage during wafer cutting. While the conventional process involves thinning the wafer by backgrinding before it is cut, DBG is a different method that partially cuts the wafer before it goes through backgrinding and completely cuts it off through mounting tape expand⁴.

⁴ Mounting tape expand (MTE): Expansion of the mounting tape that is attached to the wafer after stealth dicing, a method of creating cracks in a wafer with a laser. Physical force is then applied to the relevant areas to break the wafer into chips.

Step Three: Die Attach

As shown in Figure 4, die attach is the process of picking up the chips that have gone through the wafer cutting process from the mounting tape and attaching them to a substrate or leadframe that has been coated with an adhesive.

▲ Figure 4. The die attach process (Source: Hanol Publishing)

During the wafer cutting process, the chip that has been cut should not fall off the mounting tape. However, in the attach process, the chip must be peeled off the mounting tape. As damage might be caused during the removal of the chip if the adhesion of the mounting tape is too strong, the adhesive should maintain a strong bond during wafer cutting and then weaken when it is exposed to ultraviolet light before the attach process. At this time, only chips that pass the wafer test are detached from the mounting tape.

While the removed chips must be reattached to the substrate with adhesive, there are differences depending on the type of adhesive used. If a liquid adhesive is used, it must be applied to the substrate in advance using a syringe-like dispenser or through stencil printing⁵. On the other hand, solid adhesives are usually in the form of a tape. Also known as die attach films (DAF) or wafer backside lamination (WBL) films, solid adhesives are especially preferred when chips need to be stacked. After backgrinding is complete, a DAF is attached between the mounting tape and the back of the wafer. When the wafer is cut, the DAF is cut along with it. As the DAF and the chip attached to its back will fall off, the DAF can be glued on top of the substrate or chip.

⁵ Stencil printing: A method of printing using a stencil mask to apply paste-type materials to devices such as substrates.

Step Four: Interconnection

Interconnection refers to the electrical connections between chips, chips and substrates, and other combinations within a package. The following section will introduce two interconnection methods: wire bonding and flip chip bonding.

▲ Figure 5. The seven steps of the wire bonding process (Source: Hanol Publishing)

Wire Bonding

Wire bonding uses heat, pressure, and vibration to electrically connect chips and substrates with metal wires. The wires are usually gold (Au) as they have good electrical conductivity and ductility. Wire bonding can be compared to sewing where the thread is the wire and the needle is the capillary⁶. The wire is rolled up onto a spool like a yarn and equipped to the machinery before it is pulled out and passed through the center of the capillary to form the tail at the end of the capillary. When the electronic flame-off (EFO)⁷ gives a strong electrical spark to the wire’s tail, that part melts and solidifies to form a free air ball (FAB) that is essentially caused by surface tension.

After the FAB is created, it is attached to the chip’s pad with force to form ball bonding. When the capillary is moved toward the substrate, the wire comes out like a thread to form a loop. Stitch bonding⁸ is formed by pressing the wire against the bond finger—the part of the substrate that will make the electrical connection. The wire is then pulled back even more to form a tail, and the connection between the chip and the substrate made with wiring becomes complete after the tail is cut. This procedure is repeated on the other chip pads and the substrate’s bond fingers during the wire bonding process.

⁶ Capillary: A tool used in wire bonding machines to connect chip electrodes and lead terminals with wires.

⁷ Electronic flame-off (EFO): A process which melts a wire tip by an electrical spark to form a FAB.

⁸ Stitch bonding: The bonding of wires to a pad during the semiconductor packaging process by pressing and attaching the wires.

Flip Chip Bonding and Underfill

Flip chip bonding creates a bump on top of the chip to make an electrical and mechanical connection with the substrate. Therefore, it has better electrical properties than wire bonding. There are two types of flip chip bonding: the mass reflow (MR) process and thermocompression. MR attaches the chip with the substrate by melting the junction’s solder at a high temperature. The thermocompression process, on the other hand, applies heat and pressure to the juncture to make the connection between the chip and substrate.

Since the stress caused by the difference in the coefficient of thermal expansion⁹ (CTE) between the chip and the substrate cannot be handled by the bump alone, an underfill process that fills the space between bumps with polymer is necessary to ensure solder joint reliability. There are two main underfill processes to fill up the space between bumps: post-filling, which fills the materials after flip chip bonding, and pre-applied underfill, which fills the materials before flip chip bonding. Additionally, post filling can be divided into capillary underfill (CUF) and molded underfill (MUF) depending on the underfill method. After flip chip bonding is applied, CUF fills in the gaps between bumps by using the capillary to inject underfill material into the side of the chip. As for MUF, it allows EMC to function as an underfill by using it to fill up the spaces between bumps.

⁹ Coefficient of thermal expansion (CTE): A material property that indicates the extent to which a material expands upon heating.

Step Five: Molding

Once the chip is wire bonded or flip chip bonded, it needs to be encapsulated to protect the structure from external impact. Such protection processes include molding, sealing, and welding, but only molding is used for plastic packages. The process of molding encloses EMC, which mixes thermosetting resin¹⁰ with several inorganic materials, around parts including chips and wires to protect them from physical and chemical external impacts and to create the desired package size or shape.

¹⁰ Thermosetting resin: A stable polymer material that undergoes a polymerization reaction when heated to harden and form a polymer compound. It is primarily used for EMC that protects the electronics and electrical properties of semiconductor circuits by preventing thermal and mechanical damage in addition to corrosion.

The molding process takes place in a mold. For transfer molding, a substrate with chips connected by wire bonding is placed on both molds while an EMC tablet is placed in the middle and heat and pressure is applied. This liquidizes the solid EMC to flow into both molds and fill up the space. Transfer molding faces challenges when the gap between the chip and the top of the package gets smaller as it becomes more difficult to be filled with a liquid such as EMC. Furthermore, when the substrate gets bigger, the mold has to increase in size accordingly and it therefore becomes harder for EMC to fill the space.

In recent years, the process of transfer molding reached its limits. As the number of chip stacks has increased while a package’s thickness has generally decreased, the gap between the chip and the top of the package has continued to shrink. The size of the substrate is also growing as more chips are being processed in large batches to lower manufacturing costs. For this reason, compression molding has emerged as the solution to filling the small gap. In compression molding, the mold is pre-filled with EMC powder. When heat and pressure are applied after the substrate is placed in the mold, the EMC powder filled in the mold liquidizes and is eventually molded. In this case, the EMC immediately becomes liquid and fills the space without flowing, so there is no problem filling the small gap between the chip and the top of the package.

Step Six: Marking

Marking is a process of engraving product information such as the semiconductor type or manufacturer, in addition to patterns, symbols, numbers, or letters requested by the customer, on the surface of semiconductor packages. This proves to be important when a semiconductor product fails to operate after it is packaged as the markings can assist in tracing the cause of the product’s failure. Markings can either be engraved by burning materials such as EMC with a laser or by embossing using ink.

For plastic packages, they need to be molded before the requested information is displayed on the surface. Since laser marking is simply the act of engraving, a black EMC is usually the preferred choice as it increases the legibility of the markings. This is because color cannot be applied to the engraved characters or symbols, so it is more visible to have engravings on a black background. The remaining two steps will cover the final stages of packaging substrate packages. This is where the difference lies between the processes of substrate and leadframe packages.

Step Seven: Solder Ball Mounting

Solder balls in a substrate package do not only serve as an electrical pathway between the package and external circuitry, but they also provide mechanical connections. Solder ball mounting is the process of attaching a solder ball to a substrate pad. In the first step of the process, flux¹¹ is applied to the pad and then the solder balls are placed on the pad. Then, the reflow process melts and attaches the solder balls before the flux is washed and removed. The role of the flux here is to remove impurities and oxides from the surface of the solder balls during the reflow process. This allows the solder balls to melt uniformly and provides a clean surface. When these melted solder balls flow into a stencil on the substrate, they fill each hole in the stencil. Then, the substrate and stencil are separated but the solder balls remain on top of the substrate due to the adhesion of the flux. As there will be flux that has already been applied to the pad, the solder balls will be temporarily adhesive and attach to the pad.

¹¹ Flux: A water-soluble and oil-soluble solvent that makes solder balls adhere well to the copper of the ball land.

▲ Figure 6. The temperature profile applied during the reflow process (Source: Hanol Publishing)

The solder balls attached to the substrate pad with flux melt through the reflow process. Figure 6 shows the temperature profile applied during this process. The flux is activated in the soak zone before the solder reaches its melting temperature, removing oxides and impurities from the surface of the solder balls. While the solder balls melt and attach to the pad when it is above the melting temperature, they do not flow off completely. Instead, they form a globular shape caused by surface tension in all areas except the parts where they adhere to the metal part of the pad. As the temperature decreases, they retain their shape and solidify again.

Step Eight: Singulation

Singulation is the final process of creating a substrate package. The process involves using a blade to cut the finished substrate strips into individual packages. Once the singulation process is complete, the packages are placed on a tray for package testing and the rest of the process steps.

The various steps involved in assembling conventional packages highlight how factors such as precise alignment, optimal electrical connections, and robust protection against external damages are integral to their formation. In the next episode, wafer-level packages—the other main type of semiconductor packages—will be explored in detail.

Read articles from the Front-End Process series

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The post Semiconductor Back-End Process Episode 6: The Eight Steps of Assembling Conventional Packages first appeared on SK hynix Newsroom.

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With the opening of the 4th industrial revolution era and the spread of high technologies such as artificial intelligence (AI), 5G, and autonomous driving, the demand for high-performance and ultra-small semiconductors is exploding. Accordingly, “packaging” technology, where semiconductors become solutions to have the best performance and create high added value, is now drawing great attention.

Along with this trend, SK hynix is also focusing on securing future competitiveness by paying attention to the packaging business through active investment and continuous technology development. This time, the newsroom team met with Seung Taek Yang, KI-ILL Moon, Jinwoo Park, and Ho-Young Son – Project Leader (PL) of the SK hynix’s PKG Development Division to hear about the present and the future of SK hynix’s packaging technology including conventional package, Through-Silicon Via (TSV), and Fan-Out Wafer-Level Package (FO-WLP).

Packaging Technology Determines Future Competitiveness as the Key to Increasing the Memory Product Value

After the front-end process where circuits are formed on a wafer, semiconductor chips go through the back-end process consisting of a packaging process and a test. Although a number of fine electric circuits are integrated on a chip, the chip itself cannot perform the role of a semiconductor. The packaging process serves to connect a chip electrically to the outside so that the chip can function properly and protect it from the external environment. Also, another role of packaging is to control heat generation to ensure efficient thermal emission by semiconductors.

With the advancement of semiconductor technology which makes semiconductor products faster and more functional, thermal problems are becoming more and more serious, resulting in the greater importance of the thermal dissipation of semiconductor packages. Also, even if the chip speed is high, as the electrical connection path to the system is made during the packaging process, packaging should also be implemented at a high speed to respond to the faster chip speed. For this reason, cutting-edge packaging technology for the high-density, high-speed, low-power, small-from-factor, and high-reliability semiconductor market is crucial.

Seung Taek Yang PL

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“Packaging technology is very important for high-performance devices to perform properly. For example, to transmit and receive a large amount of data at once, numerous electric paths connected to the outside should be formed, and what plays this role is the packaging process. Packaging technology stacks multiple chips to implement a capacity of four times, 16 times, or even more compared to the conventional chips, or combines several types of chips to create a system. In other words, depending on the packaging technology, the added value of a product can highly increase. Now, it is an era where chip technology alone cannot preoccupy the future market dominance without advances in packaging technology.”

SK hynix’s Packaging Technology, How Has It Developed?

As mentioned above, semiconductor packaging plays various roles including mechanical protection, electrical connection, mechanical connection, and thermal dissipation. In detail, during the packaging process, semiconductor chips are wrapped with a packaging material such as an Epoxy Molding Compound (EMC)¹ to protect them from external mechanical and chemical impacts. In addition, the packaging process physically or electrically connects the chips to a system to supply power to operate chips, ensures input and output of signals to perform desired functions, and allows dissipation of heat generated when semiconductor products are operated.

The methods of packaging semiconductors can be largely divided into two types. One is the conventional package, which is a traditional method of applying a packaging process to individual chips separated from wafers. The other is the Wafer-Level Package (WLP), where part or all of the process is carried out at the wafer stage and later cut into single pieces.

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In the packaging field as well, SK hynix has continuously developed and created innovative products from the past to the present. The early packaging technology used in 1986, when DRAM development and production began in earnest, was the lead frame² method that connects chips and pads by using gold wires. Soon after, however, the lead frame structure faced its limit, with the improvement in the device performance. Accordingly, other structures such as the Fine-Pitch Ball Grid Array (FBGA)³ based on a substrate are applied. This type of package is a conventional package, which is mainly applied to high-density NAND or mobile DRAM products since it can stack many chips in a package.

Since then, to meet the high-performance specifications required for memory products, the existing method of the conventional package has been developed and the new method of WLP has begun to be introduced, resulting in two paths of the development of the packaging technology. In particular, WLP technology is suitable for realizing high-performance products. Since packaging in the same size as the chip is possible when using this technology, it can minimize the size of finished semiconductor products. Also, saving cost is another advantage of this technology as it does not require materials such as substrates or wires.

From 2007, SK hynix has introduced the flip chip⁴ process, a technology that combines conventional packaging and WLP in graphics DRAM that requires high performance, while applying the Redistribution Layer (RDL)⁵ process to the main memory. From 2007 to 2010, SK hynix revealed a series of memory modules to which the Wafer-Level Chip Scale Package (WLCSP)⁶ was applied for the first time in the world. Based on this technology, the company applied the 3-Dimensional Stack (3DS)⁷ and introduced a 128 GB DRAM module.

More recently, the WLP process is mainly used for products such as High Bandwidth Memory (HBM), which needs to satisfy the needs for high density and high performance, and Computing DRAM, which requires much more capacity than existing products.

In 2013, SK hynix succeeded in developing and mass-producing HBM with TSV structure for the first time in the world and mass-produced 3DS products developed for High-Density products. In 2019, the company developed HBM2E and succeeded in mass-producing it just in 10 months, preoccupying a clear advantage in the HBM market and maintaining it until now.

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Next-Generation Packaging Technology as a Growth Source of SK hynix

With the increase in the demand for high-performance and ultra-small semiconductors, packaging technology is emerging as a core technology for the next-generation semiconductors to enhance semiconductor performance and production efficiency. Accordingly, SK hynix is actively developing innovative technologies to raise the value of memory solutions by strengthening the packaging competitiveness in the fields of the conventional package, TSV, and FO-WLP.

▶ “Conventional Package” through a Total Solution of Materials, Processes, and Equipment

For a single package to implement High Density, the key is to stack chips as thin as possible, which requires high-level element technologies. In this regard, KI ILL Moon PL explained the SK hynix’s technology level by presenting an index of “chip stack count”.

KI ILL Moon PL

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“SK hynix’s packaging technology is the highest level in the industry. In the case of mobile DRAM, 16 GB is achieved by integrating 16 units of 8 Gb memory in one package. In the case of NAND, a product in which 16 layers are stacked in a package is mass-produced. In addition, SK hynix is in the process of securing element technology to apply 32-layer stacking technology to mass-produced products for the first time in the industry.”

What is the competitiveness unique to SK hynix, especially in the conventional package stage to survive in the increasingly fierce competition for miniaturization and stacking? Currently, SK hynix is preparing various solutions to maximize the performance required for each characteristic of memory products.

In computing and graphics memory, the power control function is crucial as well as high speed. To achieve this, SK hynix is preparing thermal dissipation solutions for easier power control. In terms of materials and structures, the company is developing various solutions including thermal dissipation EMC and Exposed Mold Package. Also, in the case of mobile memory where the speed determines its competitiveness, wire bonding technology is being developed to reduce signal delay or capacity.

In NAND, the complex solution of the combination of controller and DRAM determines the competitiveness. For this reason, SK hynix is developing element technologies in advance so that they can be used as needed to ensure a timely supply of various solutions to customers.

As the performance of electronic products evolves, the required level for semiconductors continues to increase as well. How can SK hynix overcome the limitations in the future? Moon PL said, “Every moment, we have been facing a limit and even now, we are facing one. However, we always have been overcoming the limit, like we are now.”

For instance, just a few years ago, it was considered impossible to reduce the chip thickness below 50 ㎛ to stack eight DRAMs. Now, however, it has become a very common technology. Moon PL said, “The reason we could overcome the limit at that time was the development of the equipment, processes, and materials that could handle thin dies. We will continue to take the lead in overcoming the limits in the future through various efforts such as boundless cooperation encompassing different functions of materials, processes, and equipment in the packaging field and seeking for a total solution.”

▶ “TSV” for Realizing High-Performance and High-Density Memory

To become a winner in the ultra-speed memory HBM market, a technology gap with competitors should be widened, going beyond the level of customer demand. To achieve this, the PKG Development Division developed an exclusive, specialized technology called Mass Reflow Molded Underfill (MR-MUF)⁸ for the first time in the world and applied it to HBM products. Based on this technology, the thermal dissipation performance has been improved by more than 10℃ compared to competitors.

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Meanwhile, TSV technology was the key to the innovative enhancement in the processing speed of HBM2E, “the world’s fastest DRAM”. SK hynix has implemented 16 GB, which is more than double compared to the previous generation by connecting eight 16 Gb DRAM chips vertically with the TSV technology. TSV is one of the WLP technologies that SK hynix is currently focusing on, and SK hynix has the highest level of TSV competitiveness in the industry.

Jinwoo Park PL

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“SK hynix has secured element technologies essential for stably handling thin wafers and stacking thin chips. We have developed the Advanced Mass Reflow method, which can stack 30㎛-thick chips in multiple layers as of today. Another competitiveness of SK hynix is the organizational power to ‘realize what we need to do’ rather than ‘realize what we can do’, based on the experience of succeeding in the HBM2E development. Our differentiated competitiveness is the process of collaborating between members and seeking a solution together even in difficult situations.”

In addition to the HBM2E, 3DS products are also one of the examples of innovation in TSV technology. Previously, the Mass Reflow (MR)⁹ process commonly used in the flip chip method had been converted to the Thermal Compression (TC)¹⁰ process for multi-layer stacking and miniaturization, but it has reached the limit of productivity. To overcome this, SK hynix applied the MR method to 3DS for the first time in the world, enabling stable production and quality control. This product is expected to be even more highly favored in the near future, since the DDR5 high-density market will be completely converted to 3DS.

SK hynix’s goal this year is to increase the TSV product line and secure profitability. To achieve this goal, company-wide efforts are being made.

Park PL said, “The core of the TSV technology is to implement stacking in a stable structure, quickly and cost-effectively. The TSV technology is applied only to HBM and 3DS products currently, but this can be extended and applied to mobile and NAND products, when high processing speed is needed. In preparation for this, we are working hard in collaboration with many other departments to proactively secure cost competitiveness.

▶ “FO-WLP”, a Packaging Technology of the Next Generation

In addition to the flagship packaging technology, SK hynix is focusing on the “Fan-Out Wafer-Level Package (FO-WLP)” as a growth source and a technology to contribute to profit generation in the future.

Wafer-Level Chip Scale Package (WLCSP) can be divided into Fan-In Wafer-Level Package (FI-WLP) and Fan-Out Wafer-Level Package (FO-WLP). Both technologies adopt a method of packaging by attaching solder balls (I/O terminals) directly onto the chip without a medium such as a substrate. As the length of wiring is reduced, the electrical characteristics are improved, and more chips can be stacked by reducing the package thickness.

Here, the “fan” refers to the chip size. When the chip size is the same as the package size and the solder balls for packages are implemented within the chip size, it is called “fan-in”. When the package size is larger than the chip size and the solder balls are implemented outside the chip as well, it is called “fan-out”.

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In the case of FI-WLP, where the chip size is just same as the package size, it has a disadvantage of having to establish a new package infrastructure when a new chip is developed, since a new chip requires a different package size even though it has the same function as the previous one. In addition, if the size of the package solder ball arrangement is larger than the chip size, the package cannot be made. It is also inefficient in that defective chips should be packaged as well, since the wafer is cut after the packaging process is completed. On the contrary, in the case of FO-WLP, there is no need to package defective chips because chips are cut first before the process. Since the package size can be adjusted, it is possible to use the existing package test infrastructure and it is easy to implement the desired package solder ball arrangement. Especially, it is advantageous in that different chips can be mounted in a single package as horizontal connection with heterogeneous chips is possible.

Ho-Young Son PL

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“FO-WLP is mainly used for packaging at least two heterogeneous devices such as packaging different System on a Chip (SoC) dies or packaging an SoC and a memory chip together. It is considered a next-generation packaging technology that will satisfy the demand for high-performance products. For this reason, many foundry companies are jumping into the back-end process technology development and expanding the market based on high technology and solid business models. SK hynix is also strengthening its investments in infrastructure related to FO-WLP technology, aiming for the company’s mid to long-term growth. Also, SK hynix is steadily preparing for the application of the FO-WLP technology for each memory application, as well as developing element technologies step by step to implement products.”

Currently, SK hynix is priorly reviewing adopting the FO-WLP to memory products. It is expected that it will significantly improve the package size and device characteristics by eliminating the need to use substrate while stacking multiple, identical chips. This will be also useful to implement a package structure that dramatically improves the performance limit of the current DRAM. Ultimately, it is expected to accelerate the development of direct packaging technology for heterogeneous devices such as memory and SoC and facilitate active participation in the semiconductor ecosystem environment.

Meanwhile, Son PL emphasized the necessity of understanding the memory system better than anything else. Based on the understanding, especially on the limitations of the current memory devices, it is important to find a solution through close cooperation between related departments to overcome such limitations, Son PL said.

In addition, he showed the determination to lead the semiconductor market in the new path based on the next-generation packaging technology.

He said, “HBM products were developed by SK hynix for the first time in the world eight years ago, and have been advanced through many trials and errors. Only recently, they have become technologically competitive and started to contribute to financial achievements. Looking back to this, you can see that it takes a long time for new technology to be adopted in the market and contribute to generating profits. This also means that if we do not prepare for the future from this moment, we will not be able to survive the rapidly changing semiconductor competition.”

Lastly, he expressed his confidence in SK hynix’s future, by saying, “We believe that we will be able to lead the market with competitive technologies if we continue to carefully prepare new technologies step by step without limiting ourselves. A number of members from various related departments, not only the PKG Development Division, are working hard together, so you can look forward to the future of SK hynix.”

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Based on the technological prowess and the experience of success that have been solidly accumulated over time, the PKG Development Division overcomes limitations and is moving toward the next step. The four PKG Development leaders, who undertake a key mission to strengthen SK hynix’s future competitiveness, delivered a message of their ambition to stakeholders.

“In the current environment, we cannot survive with the device development alone. Our way forward is to develop products that meet customers’ need in a timely manner through collaboration between the device and packaging fields. Also, even with the same product, we will need to constantly study strategies for securing differentiated advantages compared to our competitors. In that sense, we expect that packaging will play a key role. To lead the packaging field, numerous members of SK hynix are working hard even at this moment in various areas from technology development to cost reduction and customer response. You can look forward to the SK hynix’s future!”

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¹Epoxy molding compound (EMC): Thermosetting plastic with excellent mechanical and electrical insulation and temperature resistance characteristics, as a resin with relatively low molecular weight, capable of three-dimensional curing in the presence of a hardener or catalyst
²Lead frame: A lead refers to a line that comes out of an electronic circuit or a terminal of an electric component and is used to connect an electronic component to a circuit board. Lead frame refers to a shaped metal plate of an inner/outer lead used when assembling a semiconductor chip; as a thin metal plate that attaches chips cut from a wafer, leads, etc. to be used in a package are formed.
³Fine-Pitch Ball Grid Array (FBGA): As a substrate type package, a package in which a pin that serves as an electrical and mechanical connection between the package and PCB is formed of a ball-shaped solder ball is called a Ball Grid Array (BGA). Among the BGA, a package with solder balls in a small distance is called FBGA, by attaching “fine” to BGA.
⁴Flip Chip: An interconnection technology where bumps are formed on a chip’s bond pad, flipped over, and bonded to a board such as a substrate; compared to wire bonding, which is a technology that electrically connects the top of a chip and a substrate or lead frame with wires by using heat and ultrasonic waves, the mounting area and height can be reduced and the electrical characteristics can be improved.
⁵Redistribution layer (RDL): A generic term for technologies that form a metal wiring layer using the wafer-level package process method and change the position of the existing chip pad to the desired position
⁶Wafer-Level Chip Scale Package (WLCSP): Unlike conventional packaging technology, where packaging is done by cutting a wafer into chip units after the fab process is completed at the wafer level, wafer-level packaging is done as a wafer-level process rather than a chip-level process and produces a single piece of the product.
⁷3D-Dimensional Stack (3DS): In a broad sense, it refers to a package where at least two IC chips are vertically stacked. More specifically, however, it refers to a package where the inside of stacked DRAM chips is electrically connected by using TSV. 3DS memory is made into a BGA package, which is then mounted on a PCB to make a product in the form of a memory module.
⁸Mass Reflow Molded Underfill (MR-MUF): A molding compounding process that secures gap filling in the flip chip process, while performing molding at the same time
⁹Mass reflow (MR): A process where multiple devices are aligned and placed on a substrate and heated in an oven, etc., to melt solders to bond them altogether; since it is carried out all at once, the word “mass” is used in this term.
¹⁰Thermal compression (TC): A method of bonding by applying heat and pressure to the junction where flip chip bonding is performed

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