▲ Figure 1. Steps to carving out the center of a cookie to fill it with chocolate syrup

Returning to the cookie analogy in the previous episode, how can chocolate syrup be added to the middle layer of the cookies shaped like the SK hynix logo, the Wings of Happiness? The easiest way that comes to mind is to remove the middle part of the cookie to pour the chocolate syrup into it. The process of carving out the part where the chocolate syrup needs to go is equivalent to “etching” in semiconductor manufacturing. When making cookies, it involves placing a cover (acting as a photomask) with holes on top of the cookie and applying a solvent that removes the uncovered areas. Afterwards, the cover is removed from the cookie so the chocolate can be poured in. Removing the excess chocolate syrup and making another layer of the cookie on top of it will allow chocolate syrup to fill the crack in the cookie.

Going back to semiconductors, there are various types of processes used to remove materials on the wafer including rinsing and etching. Rinsing refers to washing the entire wafer to remove unwanted impurities, while etching is a process that uses a photomask to carve out the desired fine pattern.

Etching Characteristics: From Selectivity to Uniformity

As etching has many important properties, the figure below will help explain many of the terms that are related to the process.

▲ Figure 2: Characteristics of isotropic and anisotropic etching

The first term to know is “selectivity,” which is the measure of how well an etching process removes only the targeted materials. During etching, some materials which are supposed to remain on the wafer such as the photoresist can also be slowly dissolved. Therefore, high selectivity means efficiently removing only the targeted materials and minimizing the removal of the areas which are to remain.

“Directionality” refers to the direction of the etching, and this can be divided into isotropic etching and anisotropic etching. Isotropic etching occurs in all directions with the exposed part of the photoresist as the starting point, while anisotropic etching only reacts well in specific directions.

The “etch rate” is the measure of how fast etching occurs. While it is generally preferable to opt for a fast etch rate, accuracy also needs to be considered. Therefore, there needs to be a balancing act between accuracy and speed during the etching process. For example, the pressure of the gas must be lowered to increase the anisotropy of etching, but lowering the pressure leads to reducing the amount of gas that is reacted and, eventually, to the slowing down of the etching.

“Uniformity” measures how evenly etching occurs on the entire surface of the wafer. Unlike photolithography, etching exposes an entire wafer to gas. For etching to proceed, substances must be circulated by injecting reactant gas and removing by-products. However, applying this evenly to the entire wafer is a difficult task, which is why different areas on the wafer have varying etch rates.

Dry and Wet Etching

Like oxidation, etching is also divided into wet and dry. While wet oxidation involves using steam as the reactant gas, wet etching dips the wafer in a reactant liquid. This method of etching has the advantages of being fast and having a high selectivity as a chemical process. However, the nature of this method leads to the etching being strongly isotropic. The liquid moves freely and reacts with the substances when the wafer is dipped in it. This leads to low precision as parts on the back of the photoresist that are not meant to be removed are taken off quickly. Moreover, due to surface tension, the etching liquid can’t pass through the gap between the photoresist and the wafer if the gap is too small. Even if a stepper draws a fine pattern, it proves to be useless if the circuit cannot be made according to the blueprint. As a result, wet etching can’t be used in core layers of modern semiconductors.

▲ Figure 3: Liquid moving freely inside a gap during wet etching

Dry etching is a process in which a wafer applied with a photomask is exposed to gas. Some examples of this type of etching include plasma etching, sputtering, and reactive ion etching (RIE). Unlike wet etching, these processes remove materials in a variety of ways, so the anisotropic and isotropic properties cannot be clearly explained. For instance, dry etching that’s performed chemically will be isotropic and physical etching will be anisotropic. Nevertheless, as RIE became a prominent dry etching method, its properties of being highly anisotropic and reasonably quick resulted in dry etching being considered as anisotropic. The exact parameters of RIE’s mechanism to remove materials will be further explained in the next section.

Chemical and Physical Etching

In addition to dry and wet etching, the etching process can also be categorized into chemical and physical etching. The chemical method uses a substance that reacts well with the material to be removed. There are various materials on the bottom of the photoresist that need to be removed such as an oxide film formed in the oxidation process or other materials applied in the deposition process. These materials are successfully taken off with the spraying of a substance that only reacts well with these parts and not with the photoresist.

The type of etching liquid and gas differs according to the material that needs to be removed, but fluorine or chlorine-based compounds are frequently used in chemical etching. As a chemical reaction is the main mechanism of this process, it has high selectivity.

The other method is physical etching, also referred to as sputtering. This process involves high-energy particles colliding with the wafer’s surface and removing the surface of materials. When the pressure of gas–usually inert gas–is lowered and high energy is applied to it, the gas separates into positive atoms and negative electrons. After the electric field is applied towards the direction of the wafer, the atoms accelerate and collide with the wafer.

Although physical etching is quite a simple process, it does have its limitations. As low pressure equates to low amounts of gas, the etch rate is slow. Additionally, physical etching removes a large proportion of materials that should remain on the wafer as it relies on force–which doesn’t distinguish between materials. The most important method that’s used in practice is RIE which combines the two methods mentioned above. As a type of dry etching, RIE converts the gas used in etching into plasma. When strong energy is applied after injecting mixed gas–formed with substances such as reactant gas and inert gas–into the equipment, the etching gas separates into electrons, positive ions, and radicals¹⁾. Electrons are lightweight and don’t have a big impact, but positive ions can perform physical etching if they accelerate toward the direction of the wafer’s surface with an electric field. Since positive ions carry an electric charge, they are highly directional when accelerated in an electric field. Up to this point, there aren’t too many differences between RIE and physical etching.

¹⁾Radical: A highly reactive atom, molecule or ion that has at least one unpaired electron.

▲ Figure 4: Overview of the RIE process

However, positive ions produce an additional effect. They weaken the bond between the collided materials as they are highly directional due to the electric field. Consequently, they tend to collide in the red area shown in Figure 4. This causes the side area to remain strongly bonded, while the bond at the front becomes weaker. When the radicals that are highly reactive come into contact later on, the front part of the surface is etched even quicker. In the end, this increases the anisotropy of the etching.

Plasma etching technology achieves three different feats. In addition to physically etching by producing positive ions, the method weakens the material to be etched while increasing the reactivity of the gas being used in the etching. Therefore, it possesses both the advantages of high selectivity and anisotropy found in chemical and physical etching, respectively. Nevertheless, even if RIE is used, etching alone cannot create all of the intended patterns.

Etchants and Etching Gases

It becomes clear by now that the gases used in etching are crucial and that the key to etching is chemical reactions. Therefore, etchants must be picked according to the material that is meant to be removed. Major factors to consider when choosing the gas include seeing whether the resulting by-products are easily removable and knowing how fine the selectivity and reaction rates are. Compounds of the halogen family that have high reactivity rates–including fluorine, chlorine, and bromine–are commonly used.

▲ Figure 5: Types of gases for plasma etching (Source: The Understanding of the Semiconductor Manufacturing Technology, p. 443)

Large numbers of materials can be applied to the top of a wafer and etched. This next section will look at several of these important materials. Generally, silicon-based materials can be easily removed with fluorine gas. When silicon comes into contact with fluorine, it has the tendency to form silicon fluoride, which can be removed quickly as it vaporizes well.

Silicon dioxide, which is commonly used as an insulating or protective material, can also be easily removed by gas containing fluorine. But unlike pure silicon, silicon dioxide is in a stable state as it is bonded with oxygen and, thus, needs to be used with gas that produces heat. So, gases that have carbon atoms bonded to fluorine are usually used for etching. The silicon atom is taken from oxygen by the thermogenic action of the gas.

In the HKMG²⁾ and BEOL³⁾ processes, it’s necessary to etch metallic materials. While metals generally react with halogen-based gases like chlorine and fluorine, it’s notable that metals generally have by-products with high evaporation points. Therefore, it’s more difficult to remove them. For copper, the evaporation point of its by-products from reacting with gas is over 1,000 degrees Celsius. This means that copper adheres like rust. However, if the temperature of the wafer is raised to 1,000 degrees Celsius to remove these by-products, the heat can damage important devices. As a result, copper–regardless of its exceptional electrical properties–could be introduced with a new method of construction called Damascene⁴⁾ only after the electrical properties of aluminum have reached their limit. It’s important to bear in mind that a new material is not valuable in and of itself, but that it’s only valuable when a new process capable of mass production is introduced and harmonizes with existing processes.

²⁾HKMG (High-K Metal Gate): A new MOSFET gate developed to effectively reduce leakage current. A transistor where metal replaces the gate that was polysilicon and high-K replaces the insulation film that was silicon dioxide.
³⁾BEOL (Back End of Line): A process of creating extremely fine wiring to connect billions of unit devices together.
⁴⁾Damascene: A process used to create copper wiring. After etching the metal space, the metal goes under deposition and its excesses are physically removed.

Note that the above reactions are not perfectly controlled according to the type of substance. For example, gases that efficiently remove silicon can also tend to remove silicon dioxide, and vice versa. Therefore, there needs to be special attention to the mixture of gases when silicon and silicon dioxide are exposed together and it’s necessary to remove more than one specific material.

Additive gases are also critical, as adding various gases like oxygen, nitrogen, and hydrogen to the etching gas can bring about desired properties. In the case of hydrogen, it generates a lining that increases anisotropy if added during the process of removing silicon. Inert gases are also added partially. Neon gas is a prime example as it can control the concentration of the etching gas or provide the effects of physical etching.

Another Factor to Raising Density

Etching is a key step in the semiconductor manufacturing process that combines physical and chemical methods to create desired fine patterns on a wafer. Although it does not directly draw a precise pattern like a stepper, it is a very important task that helps hundreds of billions of transistors across the wafer to have nearly identical shapes. It adjusts various factors such as the gas ratio, temperature, the intensity of the electric field and pressure.

The importance of etching has grown even greater recently as the increase of density through the development of steppers has reached its limit. FinFET⁵⁾ from products such as CPUs and APs is an example of this occurrence.

DRAM and NAND, the two core products of SK hynix, rely heavily on etching. For DRAM, it has the problem of having to gradually make the capacitor higher to store more data, while more than 100 layers need to be etched to upgrade to 3D NAND memory.

These products require a very high aspect ratio⁶⁾ and, in order to ensure high reliability, there are innumerable factors that etching must solve such as having the starting point of the etching be almost identical to the diameter of the floor.

⁵⁾FinFET: A type of 3D MOSFET that has a passage of current that looks similar to the shape of a fish’s fin.
⁶⁾Aspect ratio: The value from dividing the etch depth by the etch base. The bigger the aspect ratio, the deeper the removal.

▲ Figure 6: The internal structure of DRAM. Numerous thin and deep structures in the cell area are capacitors.

As explained in this episode, silicon and silicon dioxide are very easy to remove because they vaporize and disappear immediately when they come into contact with fluorine. With this in mind, it is possible to anticipate what happens after a silicon wafer changes to germanium or another material. Germanium is of no use if it can’t be manufactured through processes like etching or deposition, regardless of how strong its properties are.

As we can see, the main etching processes are effective in removing unwanted surface materials and carving the desired pattern on the wafer’s surface. The etching process is one of the most crucial steps in the fabrication of semiconductors as a precise pattern needs to be etched to ensure the chip functions correctly.

Read articles from the Front-End Process series

Read articles from the Back-End Process series

The post Semiconductor Front-End Process Episode 4: Etching Fine and Identical Wafer Patterns first appeared on SK hynix Newsroom.

1. Aspect Ratio (A/R)

Figure 1. Concept of aspect ratio and changes in aspect ratio in accordance with technological advancement

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Aspect Ratio (A/R) is the ratio of the horizontal axis length compared to the vertical axis (height divided by width). As the critical dimension (CD) of a circuit gets smaller, the A/R value increases. That is, if the width is 10 nm when the A/R is 10, a hole with a 100 nm height should be dug out in the etching process. Therefore, for next-generation products requiring ultra-miniaturization (2D) or high density (3D), an extremely high A/R should be achieved to allow cations to penetrate the lower layer during etching.

To implement ultra-miniaturization technology with a CD less than 10 nm in 2D, the capacitor A/R of DRAM should be kept above 100. Likewise, the 3D of NAND flash also requires a high A/R to stack 256 layers or more of cells. Even if the required conditions of other processes are met, the necessary product cannot be produced unless the etching process supports it. This is why etching technology is becoming more important.

2. Overview of Plasma Etching

Figure 2. Plasma source gas by film type

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When a tube is hollow, the narrower the diameter of the tube is, the easier it gets for the liquid to enter due to the capillary phenomenon. However, it gets rather difficult if you have to dig out a hole (dead end) in the bare ground. For this reason, since the mid-70s when the circuit CD was 3 to 5 ㎛, dry etching became the trend, replacing wet etching. That is, although ionized, it is much easier to penetrate deep holes since the volume of individual molecules is smaller than that of organically agglomerated solution molecules.

In plasma etching, the inside of a process chamber where etching is to be performed should be first made into a vacuum state, before a plasma source gas suitable for the layer is injected. When etching a solid oxide film, a strong C-F-based source is used. For silicon or metal films, which are relatively weaker, a CL-based source gas is used.

Then, how should the gate layers and the underlying silicon dioxide (SiO2) insulating layers be etched?

First, in the case of gate layers, silicon is removed with a CL-based plasma (Si+ Cl2) with an etch selectivity of polysilicon. For the lower insulating layer, a two-step etching is performed with a more powerful C-F-based source gas (SiO2+CF4) with the selectivity to etch the SiO2 film.

3. Reactive Ion Etching (RIE, or Physicochemical Etching) Process

Figure 3. Strengths of RIE method (anisotropy and high etch rate)

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Plasma contains both isotropic radicals and anisotropic cations at the same time, then how does it perform anisotropic etching?

Dry etching using plasma is mostly performed in the reactive ion etching (RIE) method or an application based on the RIE method. The core of the RIE method is to weaken the binding force between the molecules of the target in the film by attacking the etching area with anisotropic cations. The weakened area is absorbed by radicals, combined with the particles constituting the layer to make them into a gas, which is a volatile compound, and release.

Although radicals are isotropic, molecules that make up the bottom surface, whose bonding force is weakened by the attack of cations, are more easily captured by radicals and turn into new compounds, than the walls with a strong bonding force. Therefore, downward etching becomes the mainstream. The captured particles turn into a gas with the radicals and are desorbed from the surface and released by the force of vacuum.

At this time, when physicochemical etching is performed by combining cations acting physically and radicals reacting chemically, the etch rate (etching degree over time) increases by 10 times compared to the case of performing cation etching or radical etching separately. With this method, the etch rate of the anisotropic downwards etching increases, resolving the issue of the polymer remaining after etching at the same time. This method is called RIE etching. The key to a successful RIE etching is to find the right plasma source gas suitable for the film to be etched. Note: Since plasma etching is RIE etching, they can be considered as the same concept.

4. Etch Rate and Core Performance Index

Figure 4. Core etching performance index related to the etch rate

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The etch rate refers to the depth of a hope when etching a film for one minute. Then, what does it mean that etch rates of various parts on a single wafer are different from each other?

This means that the depth of etching is different for each point on the wafer. For this reason, it is important to set the end of point (EOP) where etching should be stopped by considering the average etch rate and the depth of etching. Even when an EOP is set, there are still areas that are overly etched (over-etching) or insufficiently etched (under-etching) than planned. In etching, however, over-etching causes less damage than under-etching. This is because the less etched part in the case of under-etching hinders the following process such as ion implantation.

Meanwhile, selectivity, measured by etch rate, is a key performance index for etching. The criterion is the etch rate of the target layer compared to the etch rate of the layer that always plays a role in masking (PR film, oxide film, nitride film, etc.). This means that the higher the selectivity is, the faster the target layer is etched. The higher level of miniaturization requires a higher selectivity so that fine patterns can be properly realized. The selectivity of cationic etching is low since the direction is straight, but the selectivity of radical etching is high, resulting in the increased selectivity of RIE.

5. Etching Process

Figure 5. Etching Process

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First, a wafer is placed in a furnace of the oxidation process where the temperature is kept between 800 to 1,000 degrees Celsius, and then a silicon dioxide (SiO2) film with high insulating properties is formed on the wafer surface through a dry method. Then, it is moved to the deposition process to make a silicon layer or a conductive layer on the oxide film through the CVD/PVD process. If it is a silicon layer, impurities are diffused when necessary to increase conductivity. During diffusion, multiple impurities are often added repeatedly.
Now, the insulating layer and poly layer should be combined for etching. First, the photo resist (PR) is applied. Then, a mask is placed on the PR film and wet exposure is performed using an immersion method to engrave the desired pattern on the PR film (This is not visible to the naked eye). When development is performed to reveal the outline of the pattern, the PR of the photosensitive area is removed. Afterwards, the wafer that went through the photo process is transferred to the etching process to perform dry etching.

Dry etching is mainly performed in the RIE method, and it is repeatedly carried out by changing the source gas for each film. Both dry and wet etching are used to increase the A/R of etching Also, the polymer accumulated in the bottom of the holes (gaps formed by etching) is removed through periodic cleaning. What’s important is that all variables such as material, source, time, form, and order should be organically adjusted to allow the cleaning solution or plasma sources to move downwards to the bottom of the trench. Even a small change in one variable prompts recalculation of other variables, which should be repeated until the goal is met.

Recently, layers such as ALD are getting thinner and the material is getting harder. Accordingly, the etching technology is developing toward using low temperature and low pressure. The purpose of the etching is to control the CD, which makes fine patterns and ensure that there are no problems due to the action of etching, especially under-etching and the issue related to removal of residues. The most important things you should know in the two articles about etching are the purpose of etching, the obstacles to achieving that purpose, and the performance indices used to overcome those obstacles.

The post Etching, Process to Complete Semiconductor Patterning – 2 first appeared on SK hynix Newsroom.

1. Trend of Technological Development of Deposition and Etching

Figure 1. Trend of technological development of deposition and etching

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The process of forming a layer on a wafer is called deposition (CVD, ALD, and PVD) and the process of drawing a circuit pattern on the layer formed is called exposure. Etching is a process of carving the patterns on the wafers following the deposition and exposure processes. Since the photo process is like drawing a rough sketch, what really brings an apparent change to the wafers are deposition and etching processes.

There have been significant developments in both etching and deposition technologies since the birth of semiconductors. The most remarkable innovation in deposition technology was moving to a stacking method from a trench method in accordance with greater capacity of devices from 4 Megabit (Mb) DRAM from 1Mb in early 1990s. A pivotal moment for the etching technology was in early 2010s when 3D NAND flash cells were stacked in more than 24 layers. With the number of layers having increased to 128, 256, and 512 afterwards, etching has become one of the most technically difficult processes.

2. Changes of Etching Method

Figure 2. Development of etching method along with miniaturization (2D)

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The etching process has developed in accordance with the miniaturization progress of 2D (planar structure) semiconductors and the development of the stacking technology of 3D (spatial structure) semiconductors. In the 1970s, when 2D semiconductors were the mainstream, the circuit CD was rapidly decreasing from 100 micrometers (㎛) to 10 ㎛, or even lower. During this time, most of the line-up of the key process technologies of semiconductor manufacturing was finalized, while the transition of the etching technology from wet etching to dry etching was complete. For layer-cutting technology, chemical wet method, a relatively easy technique, was the first to be applied. As meeting the requirements for the 5 ㎛ of CD was difficult with the chemical wet method from early 1970s, a dry method using plasma was developed. Today, the dry method accounts for most of the etching process, while wet etching technique was later adopted and developed for the cleaning process.

3. Strengths and Weaknesses of Wet Etching and Dry Etching

Figure 3. Strengths and weaknesses of wet etching and dry etching

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With usage of a liquid, wet etching is faster, removing a greater depth per minute, but doesn’t result in a straight square-like structure. It etches all directions evenly. This leads to a loss in the lateral direction, which should be avoided for miniaturization of CD. On the contrary, dry etching allows cutting in a certain direction, making realization of the ultra-fine profile of the intended nanometer (nm) level possible.

Also, wet etching results in pollution since the used liquid should be discarded after the completion of the process. In contrast, dry etching uses a device called a scrubber in the middle of the discharge line to neutralize the exhaust gas before discharging into the air, resulting in less impact on the environment.

Meanwhile, since multiple layers are complicatedly intertwined on a wafer, it is difficult to target a certain layer (film) during etching. Wet etching is an easier option when targeting a certain film as it uses chemical reaction. It’s not easy to apply the dry method for selective etching as it’s a combination of physical and chemical techniques.

4. Etching Process Flow and Related Issues

Figure 4. Etching-related process flow

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The flow of the process starting from forming a film, applying PR on it and going through various steps like exposure, development, etching, ashing, cleaning, inspection and ion implantation is to create three TR terminals, the core process for semiconductor manufacturing. If the process of cutting the PR during the development step doesn’t go well, the remaining PR hinders etching. If a targeted layer is not sufficiently etched during the etching process, ion cannot be implanted as planned as impurity particles block. The same applies if the polymer residue remaining after dry etching is not thoroughly cleaned. If the amount of plasma ion gas is too large or a film is over-etched, due to a failure in time control, physical damage is caused on the lower film.

For this reason, it is crucial to find a precise end of point (EOP) in dry etching. It’s also important to thoroughly check the etching condition as well as the ashing and the cleaning process. A wafer could be rejected if it’s unevenly etched and under-etching is more fatal than over-etching.

Since the etching process involves complicated steps, I intend to divide the coverage into two parts. In this part, we’ve gone through the overall history and the direction of the etching technology development. We’ll look into more details of the relation between plasma and etching, RIE, one of the etching methods, the Aspect Ratio and the speed of etching in the next part.

The post Etching, Process to Complete Semiconductor Patterning – 1 first appeared on SK hynix Newsroom.