In this EE Times article, Ki-ill Moon, the head of PKG Technology Development at SK hynix, covers the evolution of packaging technology and highlights some of the company’s recent efforts and accomplishments in helping to advance the field.

As the speed, density, and functions of a semiconductor product vary depending on how the interconnection is made, interconnection methods during the packaging process are constantly changing and developing as mentioned by Moon in his previous article.

More specifically, the following four types of interconnection techniques have gradually developed over time to eventually provide more efficient and high-quality packaging techniques: wire bonding, flip chip bonding, through-silicon via¹ (TSV) bonding, and hybrid bonding with chiplets.

¹Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

With traditional wire bonding technology advancing all the way to the more recent hybrid bonding with chiplets, unprecedented achievements have been made through improvements in the package’s cost-effectiveness, operating speed, flexibility of chip design, thermal dissipation, and size reduction.

Following such developments, SK hynix developed the world’s first-ever 12-layer HBM3 in April 2023. Furthermore, the company plans to use the most high-powered packaging solution to develop hybrid bonding so it can be applied to its future HBM products such as the 16-layer HBM.

To find out more about the technologies that will help SK hynix elevate its packaging technologies and platform solutions to unprecedented levels, read the full EE Times article here: The Role of Interconnection in the Evolution of Advanced Packaging Technology

The post The Role of Interconnection in the Evolution of Advanced Packaging Technology first appeared on SK hynix Newsroom.

Packaging technology has four main functions. It protects the semiconductor chip from external shock or damage, provides external power and wiring to the chip, and properly distributes heat generated by the chip to ensure stable operation. Additionally, packaging technology acts as a bridge by connecting the gaps existing between semiconductor devices and systems.

Over the past two decades, packaging technology has evolved significantly. These developments include stacking multiple chips onto one package and including chip bumps for interconnection that shortened the signal path to achieve faster operating speeds. Most recently, packaging technology can be considered a system solution by itself as it’s capable of connecting various types of chips into one package and many parts into one module when incorporating a system.

In this EE Times article by Ki-ill Moon, head of Package Technology Development at SK hynix, the author details how SK hynix’s packaging technologies such as Chip-on-Chip (CoC) and Mass Reflow Molded Underfill (MR-MUF) produced vast improvements in speed, cost, and quality.

Today, SK hynix is leading the packaging revolution as it has been mass-producing advanced packaging products based on HBM3 and focusing on investing in production lines and securing resources for the development of future packaging technologies such as heterogenous integration and Fan-out RDL.

As SK hynix always strives to maintain its leadership position in today’s semiconductor memory industry, the company will continue to make innovative efforts to advance its packaging technologies and become a total “solution provider.”

Learn more about the evolution of packaging technology by reading the EE Times article: The Value of Semiconductor Packaging Technology in the Era of Heterogeneous Integration

The post The Value of Semiconductor Packaging Technology in the Era of Heterogeneous Integration first appeared on SK hynix Newsroom.