1. Epitaxial Layer, an “Ultra-hyper Pure” Layer over an Ultra-pure Wafer

Figure 1. Initial seed-wafer and epitaxial layer with additional processing

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Wafers are manufactured in the wafer manufacturing process, separately from the semiconductor manufacturing process. When transforming molten silicon into an ingot of high purity close to 100% and cutting it into a plate shape, wafers are completed. For wafers, various materials are used, ranging from silicon, which is most frequently used for integrated circuits, and germanium, to gallium arsenide for high-speed analog use.

Most wafer manufacturing processes have a similar flow in general, though some of them are slightly different in terms of process conditions and methods. Silicon wafers are categorized into three: ultra-pure wafers, impurity (P/N type) wafers, and epitaxial wafers with additional processes. Among these, silicon wafers doped in p-type are most commonly used. This is because CMOSFETs can be simply manufactured as soon as N-Well (semiconductor manufacturing process) is formed on a P-type substrate. Epitaxial wafers, or epi wafers, are completed after going through an additional process called the epitaxial process where ultrapure wafers are used as a seed (medium).

2. Prerequisite of Epitaxial Layer: Crystalline Structure

Figure 2. Epitaxial layer vs Amorphous layer

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The prefix “epi-” means ‘upon’ or ‘on top of’ and epitaxial refers to a layer made in the upper direction. Epitaxial growth can be also called epitaxy or epi in short. This means stacking additional new layer with the growth into a single crystal, which is a solid where all crystals of one type are regularly generated along a certain crystal axis, while a seed wafer is placed underneath and the lattice direction is maintained.

In the transistor structure, substrates that serve as the paths for the flow of drain currents, should have a crystalline structure; however, since most of the deposition methods used in the early semiconductor manufacturing process have noncrystalline (amorphous) layers, special conditions and methods should be adopted to make epitaxial layers grow to avoid an amorphous state.

To be used as a seed-layer, the lattice composition should be crystalline, while inheriting the crystal lattice structure of the lower layer for upward growth. Therefore, it is necessary to have a layer where the alignment of the lattice is regular and the lattice constants are consistent or almost similar. Here, a new layer or substrate formed by a special method on the seed-layer is called an epitaxial layer, and a wafer on which an epitaxial layer is formed is called an epitaxial wafer.

3. Conditions for Electron Flow within Crystal Lattice

One of the functions of semiconductor components is to move electrons, detect and judge the movement, and use the judgment result as On/Off information. The reason for adding another process (ultra-hyper pure) on the seed-wafer is to make a layer with no defect to facilitate electrons’ move in the zero-defect field.

To increase mobility of electrons in a certain direction, the crystal lattice should be regularly arranged. It is better if the distance between atoms is constant. In other words, polycrystalline or noncrystalline (amorphous) lattice arrangement weakens electron mobility and causes electron traps, making it difficult to predict and manage the gate voltage and drain current.

4. Crystal Lattice Constant

Figure 4. Lattice constants of the epitaxial layer and single-crystal structure

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A lattice constant refers to the distance of the bonds (covalent bonds) between silicon atoms. Any entry of a third element in the middle leads to a change in the quantity of electric charge, resulting in a change in the distance between atoms (lattice constant). It is important to maintain the lattice constant little changed if possible. If the inconsistent lattice constant results in a change in thermal expansion coefficient of the upper and lower layers, it could cause a wafer warpage. Also, when stacking SiO2 or HfO2 as a gate oxide layer, stacking an oxide layer over an ultra-hyper pure layer with a crystal lattice constant unified through epitaxial growth, rather than over a partly impure silicon substrate, can minimize electron traps between interfaces and mismatches (weakened adhesion, etc.) between interfaces.

Despite its excellent quality, epitaxial layers are used only in special cases due to the complicated process and high cost. In particular, as the epitaxial process requires growth in a single crystal, the speed of processing is slow.

5. Lattice Match & Mismatch

When a seed-layer and an epitaxial layer have the same distance in the crystal structure, we call it homoepitaxy, and when it is not, we call it heteroepitaxy. In the case of heteroepitaxy, when the crystal lattice distance of the epitaxial layer is larger, compressive stress is applied to match it to the seed-layer distance. On the contrary, when the crystal lattice distance is smaller than that of the lower layer, tensile stress is applied to increase the distance.

The form where atoms are combined is called a crystal structure or a lattice. If there is a mismatch in the distances between atoms within the crystal structure, unwanted defects such as voids and hillocks are caused, resulting in quality issues. Any dislocation or electron trap can be avoided if a new epitaxial substrate is grown on the substrate. On top of this, if the epitaxial layer is doped while being formed, a layer can be created in a desired type of impurity, allowing it to be used as a substrate for forming semiconductor components.

The post Stacking Ultra-hyper Pure Layer over Ultra-pure Wafer: Epitaxy Technology first appeared on SK hynix Newsroom.

1. Aspect Ratio (A/R)

Figure 1. Concept of aspect ratio and changes in aspect ratio in accordance with technological advancement

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Aspect Ratio (A/R) is the ratio of the horizontal axis length compared to the vertical axis (height divided by width). As the critical dimension (CD) of a circuit gets smaller, the A/R value increases. That is, if the width is 10 nm when the A/R is 10, a hole with a 100 nm height should be dug out in the etching process. Therefore, for next-generation products requiring ultra-miniaturization (2D) or high density (3D), an extremely high A/R should be achieved to allow cations to penetrate the lower layer during etching.

To implement ultra-miniaturization technology with a CD less than 10 nm in 2D, the capacitor A/R of DRAM should be kept above 100. Likewise, the 3D of NAND flash also requires a high A/R to stack 256 layers or more of cells. Even if the required conditions of other processes are met, the necessary product cannot be produced unless the etching process supports it. This is why etching technology is becoming more important.

2. Overview of Plasma Etching

Figure 2. Plasma source gas by film type

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When a tube is hollow, the narrower the diameter of the tube is, the easier it gets for the liquid to enter due to the capillary phenomenon. However, it gets rather difficult if you have to dig out a hole (dead end) in the bare ground. For this reason, since the mid-70s when the circuit CD was 3 to 5 ㎛, dry etching became the trend, replacing wet etching. That is, although ionized, it is much easier to penetrate deep holes since the volume of individual molecules is smaller than that of organically agglomerated solution molecules.

In plasma etching, the inside of a process chamber where etching is to be performed should be first made into a vacuum state, before a plasma source gas suitable for the layer is injected. When etching a solid oxide film, a strong C-F-based source is used. For silicon or metal films, which are relatively weaker, a CL-based source gas is used.

Then, how should the gate layers and the underlying silicon dioxide (SiO2) insulating layers be etched?

First, in the case of gate layers, silicon is removed with a CL-based plasma (Si+ Cl2) with an etch selectivity of polysilicon. For the lower insulating layer, a two-step etching is performed with a more powerful C-F-based source gas (SiO2+CF4) with the selectivity to etch the SiO2 film.

3. Reactive Ion Etching (RIE, or Physicochemical Etching) Process

Figure 3. Strengths of RIE method (anisotropy and high etch rate)

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Plasma contains both isotropic radicals and anisotropic cations at the same time, then how does it perform anisotropic etching?

Dry etching using plasma is mostly performed in the reactive ion etching (RIE) method or an application based on the RIE method. The core of the RIE method is to weaken the binding force between the molecules of the target in the film by attacking the etching area with anisotropic cations. The weakened area is absorbed by radicals, combined with the particles constituting the layer to make them into a gas, which is a volatile compound, and release.

Although radicals are isotropic, molecules that make up the bottom surface, whose bonding force is weakened by the attack of cations, are more easily captured by radicals and turn into new compounds, than the walls with a strong bonding force. Therefore, downward etching becomes the mainstream. The captured particles turn into a gas with the radicals and are desorbed from the surface and released by the force of vacuum.

At this time, when physicochemical etching is performed by combining cations acting physically and radicals reacting chemically, the etch rate (etching degree over time) increases by 10 times compared to the case of performing cation etching or radical etching separately. With this method, the etch rate of the anisotropic downwards etching increases, resolving the issue of the polymer remaining after etching at the same time. This method is called RIE etching. The key to a successful RIE etching is to find the right plasma source gas suitable for the film to be etched. Note: Since plasma etching is RIE etching, they can be considered as the same concept.

4. Etch Rate and Core Performance Index

Figure 4. Core etching performance index related to the etch rate

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The etch rate refers to the depth of a hope when etching a film for one minute. Then, what does it mean that etch rates of various parts on a single wafer are different from each other?

This means that the depth of etching is different for each point on the wafer. For this reason, it is important to set the end of point (EOP) where etching should be stopped by considering the average etch rate and the depth of etching. Even when an EOP is set, there are still areas that are overly etched (over-etching) or insufficiently etched (under-etching) than planned. In etching, however, over-etching causes less damage than under-etching. This is because the less etched part in the case of under-etching hinders the following process such as ion implantation.

Meanwhile, selectivity, measured by etch rate, is a key performance index for etching. The criterion is the etch rate of the target layer compared to the etch rate of the layer that always plays a role in masking (PR film, oxide film, nitride film, etc.). This means that the higher the selectivity is, the faster the target layer is etched. The higher level of miniaturization requires a higher selectivity so that fine patterns can be properly realized. The selectivity of cationic etching is low since the direction is straight, but the selectivity of radical etching is high, resulting in the increased selectivity of RIE.

5. Etching Process

Figure 5. Etching Process

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First, a wafer is placed in a furnace of the oxidation process where the temperature is kept between 800 to 1,000 degrees Celsius, and then a silicon dioxide (SiO2) film with high insulating properties is formed on the wafer surface through a dry method. Then, it is moved to the deposition process to make a silicon layer or a conductive layer on the oxide film through the CVD/PVD process. If it is a silicon layer, impurities are diffused when necessary to increase conductivity. During diffusion, multiple impurities are often added repeatedly.
Now, the insulating layer and poly layer should be combined for etching. First, the photo resist (PR) is applied. Then, a mask is placed on the PR film and wet exposure is performed using an immersion method to engrave the desired pattern on the PR film (This is not visible to the naked eye). When development is performed to reveal the outline of the pattern, the PR of the photosensitive area is removed. Afterwards, the wafer that went through the photo process is transferred to the etching process to perform dry etching.

Dry etching is mainly performed in the RIE method, and it is repeatedly carried out by changing the source gas for each film. Both dry and wet etching are used to increase the A/R of etching Also, the polymer accumulated in the bottom of the holes (gaps formed by etching) is removed through periodic cleaning. What’s important is that all variables such as material, source, time, form, and order should be organically adjusted to allow the cleaning solution or plasma sources to move downwards to the bottom of the trench. Even a small change in one variable prompts recalculation of other variables, which should be repeated until the goal is met.

Recently, layers such as ALD are getting thinner and the material is getting harder. Accordingly, the etching technology is developing toward using low temperature and low pressure. The purpose of the etching is to control the CD, which makes fine patterns and ensure that there are no problems due to the action of etching, especially under-etching and the issue related to removal of residues. The most important things you should know in the two articles about etching are the purpose of etching, the obstacles to achieving that purpose, and the performance indices used to overcome those obstacles.

The post Etching, Process to Complete Semiconductor Patterning – 2 first appeared on SK hynix Newsroom.

1. Trend of Technological Development of Deposition and Etching

Figure 1. Trend of technological development of deposition and etching

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The process of forming a layer on a wafer is called deposition (CVD, ALD, and PVD) and the process of drawing a circuit pattern on the layer formed is called exposure. Etching is a process of carving the patterns on the wafers following the deposition and exposure processes. Since the photo process is like drawing a rough sketch, what really brings an apparent change to the wafers are deposition and etching processes.

There have been significant developments in both etching and deposition technologies since the birth of semiconductors. The most remarkable innovation in deposition technology was moving to a stacking method from a trench method in accordance with greater capacity of devices from 4 Megabit (Mb) DRAM from 1Mb in early 1990s. A pivotal moment for the etching technology was in early 2010s when 3D NAND flash cells were stacked in more than 24 layers. With the number of layers having increased to 128, 256, and 512 afterwards, etching has become one of the most technically difficult processes.

2. Changes of Etching Method

Figure 2. Development of etching method along with miniaturization (2D)

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The etching process has developed in accordance with the miniaturization progress of 2D (planar structure) semiconductors and the development of the stacking technology of 3D (spatial structure) semiconductors. In the 1970s, when 2D semiconductors were the mainstream, the circuit CD was rapidly decreasing from 100 micrometers (㎛) to 10 ㎛, or even lower. During this time, most of the line-up of the key process technologies of semiconductor manufacturing was finalized, while the transition of the etching technology from wet etching to dry etching was complete. For layer-cutting technology, chemical wet method, a relatively easy technique, was the first to be applied. As meeting the requirements for the 5 ㎛ of CD was difficult with the chemical wet method from early 1970s, a dry method using plasma was developed. Today, the dry method accounts for most of the etching process, while wet etching technique was later adopted and developed for the cleaning process.

3. Strengths and Weaknesses of Wet Etching and Dry Etching

Figure 3. Strengths and weaknesses of wet etching and dry etching

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With usage of a liquid, wet etching is faster, removing a greater depth per minute, but doesn’t result in a straight square-like structure. It etches all directions evenly. This leads to a loss in the lateral direction, which should be avoided for miniaturization of CD. On the contrary, dry etching allows cutting in a certain direction, making realization of the ultra-fine profile of the intended nanometer (nm) level possible.

Also, wet etching results in pollution since the used liquid should be discarded after the completion of the process. In contrast, dry etching uses a device called a scrubber in the middle of the discharge line to neutralize the exhaust gas before discharging into the air, resulting in less impact on the environment.

Meanwhile, since multiple layers are complicatedly intertwined on a wafer, it is difficult to target a certain layer (film) during etching. Wet etching is an easier option when targeting a certain film as it uses chemical reaction. It’s not easy to apply the dry method for selective etching as it’s a combination of physical and chemical techniques.

4. Etching Process Flow and Related Issues

Figure 4. Etching-related process flow

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The flow of the process starting from forming a film, applying PR on it and going through various steps like exposure, development, etching, ashing, cleaning, inspection and ion implantation is to create three TR terminals, the core process for semiconductor manufacturing. If the process of cutting the PR during the development step doesn’t go well, the remaining PR hinders etching. If a targeted layer is not sufficiently etched during the etching process, ion cannot be implanted as planned as impurity particles block. The same applies if the polymer residue remaining after dry etching is not thoroughly cleaned. If the amount of plasma ion gas is too large or a film is over-etched, due to a failure in time control, physical damage is caused on the lower film.

For this reason, it is crucial to find a precise end of point (EOP) in dry etching. It’s also important to thoroughly check the etching condition as well as the ashing and the cleaning process. A wafer could be rejected if it’s unevenly etched and under-etching is more fatal than over-etching.

Since the etching process involves complicated steps, I intend to divide the coverage into two parts. In this part, we’ve gone through the overall history and the direction of the etching technology development. We’ll look into more details of the relation between plasma and etching, RIE, one of the etching methods, the Aspect Ratio and the speed of etching in the next part.

The post Etching, Process to Complete Semiconductor Patterning – 1 first appeared on SK hynix Newsroom.

1. Semiconductors from the Perspective of Current

The criterion that distinguishes between conductors and insulators is the “flow of current”. If a current flows, it is a conductor, and if it doesn’t, it is an insulator. Then, how much current should flow exactly in a semiconductor, as a concept between a conductor and an insulator? 10 [A] or 10 [mA]? 10 [nA] or 10 [pA]? No one can give the right answer to this. This is because the meaning of “an electric current flows in half” is only literary rhetoric, and is not defined scientifically.

Nevertheless, dichotomous rules such as “flowing (ON)” and “not flowing (OFF)” make sense both literally and scientifically, so it is reasonable to define conductors and insulators. In this sense, semiconductors, meaning half-“flowing”, are included in the “flowing (ON)” category, so they should be considered as “conductors”. Thus, in terms of current, semiconductors would have to be included in the category of conductors. Then, what is the reason for distinguishing semiconductors from conductors?

2. “Doping” to Change Insulating Material to Conductive Material

<Figure 1>Correlation of insulating and conductive functions of semiconductors according to changes in resistivity (Refer to the book “Basic Insight NAND Flash Memory” by Jong-moon Jin)

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The reason is that, when it comes to distinguishing between conductors, semiconductors, and insulators, the influence of the “material property” is greater than the influence of properties or operations of the object. Among the materials on Earth, especially pure germanium and silicon, which are Group 14 elements, are insulating materials; however, when a Group 13 or Group 15 element is chemically mixed (doped) with a Group 14 element and bonded with the Group 14 element (sharing atoms and outermost electrons), the conductivity (σ) increases. In other words, the resistivity (ρ), which means the degree to which electricity cannot pass through, decreases accordingly. It means a breakthrough technological innovation where the amount of current can be controlled as desired while managing the doping concentration freely at the same time. As this shows, the charm of semiconductors is that they convert pure silicon insulators into conductive materials through doping (diffusion or ion-implantation method).

At this time, the conductivity or resistivity is determined according to the doping amount, and the material doped to have a medium resistivity value lower than an insulating material and higher than a conductive material is called a semiconductor. This material has many types such as a substrate (N-type/P-type substrate), a well (N-type/P-type), a source/drain terminal (N-type/P-type), a poly-gate terminal, and other minor layers. Semiconductors are sometimes used as conductive objects or insulating objects. For this reason, defining semiconductors as a material used as a “half conductor” is rather vague. From three to four years ago, a material called CTF with a concept of half conductor is sometimes used when confining (storing) electrons in 3D-NAND, but except for these cases, semiconductors function as conductors or insulators.

3. Resistivity for Distinguishing between Conductors, Semiconductors, and Insulators

<Figure 2>Four constants affecting semiconductors

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Semiconductors can be expressed and classified by many variables and constants, but it is convenient to express them with constants when distinguishing the material property from insulators or conductors. Among various constants to describe a semiconductor, conductivity, permittivity, or permeability that are considered in the semiconductor is complicated in that electrical or magnetic properties should be derived by inputting variables (variables such as the strength of electric field or magnetic field).

When using the constant ρ of the resistivity <R=ρ (length/area)>, however, the three-dimensional volume (length and area) and material properties of a semiconductor can be derived from fixed values (constants). Also, it has the advantage of not being easily influenced by other values other than temperature. The resistivity of semiconductors can be classified in a range of 10^-4 to 10^2 Ω⋅m, which makes it convenient to express the properties of the material (The ranges are slightly different by data); however, these resistivity values are also variable with the changes in temperature.

4. What is a Semiconductor?

<Figure 3>Internal structure of TR and resistivity @ Old model structure

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In conclusion, a semiconductor is an object with a lowered resistivity constant of the material to about 10^-4 to 10^2 Ω⋅m by chemically bonding (doping) impurity elements of Group 13 or Group 15 to pure silicon, an insulating material. This doping method determines the resistivity or conductivity constant of both non-memory and memory devices by allowing each material or layer to have its own constant. The charge moves easily or hardly according to the extent calculated in advance by the values of these constants, which also affect the ability to capture or store electrons. Memory devices are also influenced by dielectric constant (proportional charge accumulation) or permeability constant (proportional magnetic flux density).

Therefore, the quantity of drain current and the number of electrons captured in the capacitor of a DRAM and the floating gate of a NAND are determined by adjusting the four constants mentioned – resistivity, conductivity, permittivity, and permeability. Also, the influence of the external current flow on the captured or flowing electrons should be minimized (By calculating the value and changing the structure or material accordingly, the flow of electrons and the number of electrons are prevented from experiencing rapid changes). Eventually, by adjusting the amount of doping and structural forms that change the material of a layer, the four constants have appropriate values so that the device made by combining semiconductors can perform the function of ON/OFF properly.

Insulators have various materials such as oxidized materials, nitride materials, and silicon-based materials (gallium arsenide semiconductors, etc.). Among them, semiconductors made of a material with the desired conductivity through doping on an insulator of a pure silicon material are representative. Once doping is performed, the doping amount doesn’t change, and the “resistivity” value is fixed in reverse proportion accordingly. In short, a semiconductor can be explained as a conductor where the resistivity value has been changed by doping impurity of Group 13 or Group 15 in insulating silicon. There is no semiconductor which is a half conductor. While alchemy to convert non-gold materials to gold eventually had failed despite countless attempts for a long time, it can be said that a kind of transformed alchemy of the 20th century has succeeded with the birth of doped semiconductors.

The post Definition of Semiconductors first appeared on SK hynix Newsroom.

※ Encapsulation, sealing, airtight sealing, etc. have similar meanings. In this article, encapsulation is regarded as a concept of a larger category, and sealing is limited to molding.

1. Package Encapsulation Method by Encapsulant

Figure 1. Comparison between hermetic method and molding method

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Packages encapsulated in a hermetic method using ceramic or metal have the advantage of being durable with a long life. For this reason, this method is mainly applied to devices in special fields, such as national defense and medical care. Representative product types include CPU, Erasable Programmable Read-Only Memory (EPROM, non-volatile semiconductor memory chip), and Power TR (large output transistor used for power).

The hermetic method is highly reliable but it is expensive. For this reason, the molding method using a plastic epoxy material is widely used. In the case of plastics, the range of use is rapidly expanding with the continuous improvement of defects such as moisture and internal voids. From EPROM, plastic materials are used for sealing in almost all cases and are applied to most packages including DRAM, CPU, and NAND.

To give a simple explanation for understanding, the hermetic method is like the method of attaching concrete panels made in advance at the factory to the exterior wall of a building, while the molding method is like the method of making a formwork and pouring concrete at the construction site. While the molding method is a method with improved flexibility, the possibility of pores occurring in the concrete is higher than the hermetic method.

2. Molding Material: Epoxy Molding Compound (EMC)

Epoxy molding compound (EMC), one of the essential functional materials required for the semiconductor back-end process, is a type of plastic. EMC consists mostly of a resin-based material, and the rest is composed of a mixture of filler and hardener. Epoxy in a powder compound form melts and becomes less viscous when dissolved into a gel state at a temperature of 175℃. When the temperature is lowered after, the epoxy cures, and the viscosity starts to increase in inverse proportion to the temperature. When the temperature is further lowered at this point, the epoxy shows strong bonding strength with the surrounding printed circuit boards (PCBs), lead frames, wires, wafers, etc., and becomes a material with a very high level of hardness. This material is called a thermosetting epoxy. After curing, it is important to control the EMC to consistently expand and contract similar to the chip when the temperature fluctuates, while the semiconductor is operating. Also, it is important to let the heat dissipate to the outside. Therefore, it can be said that the properties of the mixture determine the reliability of EMC.

3. Type of Molding Process

Figure 2. Molding process: transfer molding and compression molding

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Molding means making something into a certain shape. When molding a semiconductor, EMC is melted and injected into the cavity. The key of a molder, the machine responsible for molding, is the molder plate. Molding methods include transfer molding, which is an old method, vacuum molding, which is an advanced method that compensates for the disadvantages of transfer molding, and compression molding, which faces down the wafer vertically.

3-1. Transfer Molding

Figure 3. Transfer molding

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Transfer molding uses resin, as an early method of molding. In this method, the epoxy is melted in a gel state and then a certain pressure (plunging) is applied forcibly to allow it to move through multiple narrow paths. As chips became smaller and more multi-layered, and the wire bonding structure became more complex, the epoxy could not spread evenly during molding, causing incomplete molding or increased occurrence of voids or porosities. In other words, controlling the speed of epoxy became more difficult.

To solve this problem, when moving the epoxy through a narrow path, a method of creating a vacuum and pulling it out from the other side is used to control the speed of the epoxy. Also, various efforts are being made to reduce voids by allowing the epoxy to spread evenly.

3-2. Compression Molding

Figure 4. Compression Molding

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As the number of chip layers increased (Multi Chip Package, MCP) and wire bonding became more complicated, transfer molding gradually revealed its limitations. In particular, due to the larger size of carriers (PCBs or lead frames) for cost reduction, transfer molding became more difficult. Along with this, as it was difficult for the epoxy to penetrate the complex structure and spread further, a new method was needed.

Compression molding is a new method that overcomes the limitations of transfer molding, as a method in which EMC is first placed in a mold and then melted. When applying the compression molding method, there is no need to transfer the epoxy far away. It is a method of molding by vertically lowering (facing down) the wafer on the epoxy in a gel state. This method reduces defects such as voids and sweep phenomena and is positive for the environment by reducing the unnecessary use of the epoxy.

For molding the semiconductor by using epoxy, the transfer method and compression method are being used together. The compression method is highly preferred by suppliers for its advantages such as defect detection, cost reduction, and minimization of environmental impact. As customers’ needs for product flattening and thinning are increasing, it is expected that the compression method will be used more actively in the future.

The post Encapsulation Process, A Way of Sealing Packages first appeared on SK hynix Newsroom.

Figure 1. Development of bonding methods: Wire Bonding → Flip Chip Bonding → Through-Silicon Via (TSV)

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For a semiconductor chip to operate normally in various fields, a bias voltage and input should be supplied from the outside. To do this, the bonding pads of chips should be connected to wires. The method of connecting wires started with soldering in the early days and has developed in various ways from 1965 to recent times including wire bonding, flip chip bonding, and TSV. Wire bonding uses fine wires for connection while flip chip bonding uses bumpers instead of wires to increase the flexibility of the wire connection. TSV, an approach with a completely new concept, allows the upper and lower chips to be interconnected with a printed circuit board (PCB) through hundreds of holes.

2. Comparison of Bonding Methods: Wire Bonding and Flip Chip Bonding

Figure 2. Process of wire bonding and flip chip bonding

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Die bonding performed after the dicing process is a process to fix a chip to a substrate, and wire bonding after die bonding is performed to secure electrical signals. Another connection method similar to wire bonding is flip chip bonding. ▶ Refer to <Die Bonding, Process for Placing a Chip on a Package Substrate> Both of these methods connect the bonding pads in chips and the pads on PCBs using metallic objects with a small diameter (in the case of a lead frame, it is used only in wire bonding). Wires in wire bonding have several disadvantages. As the length is longer and the diameter is smaller compared to bumps, it takes a long time to transmit an electrical signal and the signal can be easily distorted due to the high impedance of the wires. Also, the solder neck is easily disconnected or the bonding strength is weak, resulting in poor tensile strength. On the contrary, flip chip bonding has many advantages in connection reliability and electrical signal transmission even though it is more complicated to handle because the solder balls used as connectors are very small.

3. What is Wire Bonding?

Figure 3. Structure of wire bonding (When the carrier is a printed circuit board (PCB))

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Wire bonding is a method of bonding thin metal wires to a pad, as a technology that connects the internal chip and the outside. In terms of structure, wires act as a bridge between the bonding pad of the chip (first bond) and the pad of the carrier (second bond). While lead frames were used as carrier substrates in the early days, PCBs are more frequently used now with the advancement of technology. Wire bonding, which connects two pads separated from each other, can vary greatly in terms of wire material, bonding conditions, and bonding location – not only between a chip and a substrate, but also between two chips or between two substrates).

4. Wire Bonding Methods: Thermo-Compression / Ultrasonic / Thermosonic

Figure 4. Wire bonding methods

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There are three main ways to connect wires to pads, which include the following: The thermo-compression method where the bonding pad and capillary, a capillary-like tool for wire transfer, are heated and compressed for connection; a method of bonding, by applying ultrasonic waves to the capillary without using heat; and a complex method that uses both heat and ultrasonic waves at the same time. In the first method, which is the thermo-compression bonding method, the temperature of the bonding pad of the chip is raised to about 200℃ in advance. Then, the temperature of the tip of the capillary is also raised to make the wire into a ball, thereby applying pressure to the bonding pad through the capillary to attach the wire to the bonding pad.

Secondly, the ultrasonic method is a method of attaching the wire to the pad by applying ultrasonic waves to the wedge, which is a tool transferring wires like a capillary, but without forming a ball, while pinning down the wires against the pad surface. This method has the advantage of low cost in terms of process and material; however, since it uses ultrasonic waves which are easy to handle, instead of heat and pressure, the bonded tensile strength, the strength to withstand when the wire is pulled after wiring, is comparatively weak.

The most commonly used method in the semiconductor process is the thermosonic method, which combines the advantages of the thermos-compression method and the ultrasonic method. This method applies heat, pressure, and ultrasonic waves to the capillary to allow bonding in the optimal condition. Since the bonding strength is more important than the cost in the semiconductor back-end process, the thermosonic method using gold wires is mainly adopted despite the high cost.

5. Bonding Wire Materials: Gold (Au) / Aluminum (Al) / Copper (Cu)

The material of wires is determined by combining the most suitable methods considering various parameters for bonding. These parameters are very diverse, such as the type of semiconductor product, package type, bonding pad size, wire diameter, the bonding method, and the tensile strength and elongation of the wire, which are related to the reliability. Typical wire materials include gold (Au), aluminum (Al), and copper (Cu). Among them, gold is mostly used for semiconductor packaging.

Gold wires allow good current flow and are chemically stable which makes them resistant to corrosion. On the contrary, aluminum, which was frequently used as a wire material in the early days, had the disadvantage of being vulnerable to corrosion. Also, gold wires have adequate hardness, allowing that balls are well formed in the first bond and a semi-circular loop, the shape of the wire from the first bond to the second bond, is properly formed in the second bond.

Aluminum wires have a larger diameter, resulting in a wider pitch. While gold wires do not break when forming a loop even if high purity gold is used; pure aluminum wire breaks easily during looping. For this reason, alloys containing silicon or magnesium are mainly used. Also, aluminum wires are suitable for a high-temperature package such as hermetic, or for ultrasonic methods where gold wires cannot be used.
Copper wires are inexpensive, but the hardness is too high, which is a big disadvantage. When the hardness is high, balls are not formed well and there are many restrictions on looping. Also, since high pressure should be applied to the pad of the chip during ball bonding of the wire, cracks are more likely to occur on the film in the bottom of the pad. In addition, “peeling” may occur in which the layer of the firmly wired pad peels off; however, as the metal wiring of the chip is made of copper, there is a trend to use copper wires more often. Also, to overcome the shortcomings of copper, copper wires are applied by alloying with a small amount of other materials.

6. Wire Bonding by Material: Gold Wire vs Aluminum Wire

The most essential device in wire bonding is the capillary. Gold wires are mainly used when using it, whereas wiring is done by using a wedge when using aluminum wires. Capillary performs wiring by forming balls, but wedges do the same without having to form balls. Wedges are also different in shape from the capillary at the end of the wafer, and also differ in the way the wires are bonded and torn.

While gold wires take the option of thermosonic-capillary-ball bonding, aluminum wires perform aluminum wedge wire bonding with the option of ultrasonic-wedge bonding. The aluminum-ultrasonic method is used only in special cases due to its low tensile strength, and more than 90% of the wiring is performed in the gold-thermosonic method; however, since the thermosonic method also has the disadvantage of a weak ball neck, heat affected zones (HAZs), wire areas recrystallized while solidifying after the wire material is weakly melted by the high temperature of the capillary, should be managed carefully.

7. Ball Bonding Using Gold Wires

Figure 5. First bond: wire ball bonding on the chip’s bonding pad

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Thermosonic gold ball wire bonding, which is the most widely used among the wiring methods, includes two stages of bonding. In the first bond, the gold wire passes through the hole in the center of the capillary, and when the temperature is raised at the end of the wire, the gold melts and forms a gold ball. After that, heat, pressure, and ultrasonic vibrations are applied while opening the clamp that holds and releases the wire. When the capillary is touched to the bonding pad, the formed ball is bonded to the heated bonding pad. After the first ball bonding, the capillary is raised to the position slightly higher than the pre-measured looping height and moved to the pad for the second bond to form a loop.

Figure 6. Second bond: wire stitch bonding on the PCB’s pad

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In the second bond, when heat, pressure, and ultrasonic vibration are applied to the capillary and the balls formed for the second time are crushed on the PCB pad, stitch bonding is formed. After stitch bonding, when the wire is torn in succession, it is finished with the process of tail bonding where the tail of the wire is formed weakly. After that, the capillary closes the clamp (wire holding) and tears the wire, completing the second gold wire ball bond.

Today, we looked at how the bonding method and material of wire bonding affect each other and how the wires are bonded. In this article, the reliability and the problems that can arise during wire bonding were mentioned briefly; however, what is important in wire bonding is to understand the vulnerability, solutions developed to overcome the vulnerability, and the mutual trade-off relationship. Also, it is recommended to take a look at how the bonding method has changed with the development of the package type and packaging technology.

The post Wire Bonding, a Way to Stitch Chips to PCBs first appeared on SK hynix Newsroom.

1. What is Bonding?

Figure 1. Type of Bonding

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In the semiconductor process, “bonding” means attaching a wafer chip to a substrate. Bonding can be divided into two types, which are conventional and advanced methods. The conventional method includes die bonding (or die attach) and wire bonding, while the advanced method includes flip chip bonding developed by IBM in the late 60s. Flip chip bonding is a method combining die bonding and wire bonding, and is a method of connecting a chip and a substrate by forming bumps on the chip pad.

Just as an engine is mounted on a vehicle to supply power, die bonding electrically connects a chip and the outside, by bonding a semiconductor chip onto a lead frame or a printed circuit board (PCB). After die bonding, the chip should endure the physical pressure generated after packaging and should be able to dissipate the heat generated during the operation of the chip. When necessary, it must maintain constant electrical conduction or realize a high level of insulation. Therefore, bonding methods are becoming more important as chips continue to become smaller and smaller.

2. Procedure of Die Bonding

Figure 2. Comparison between die bonding and flip chip bonding

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For die bonding, the first thing to do is to dispense an adhesive on the package substrate. Then, a chip is placed on it, with the top side facing up. On the contrary, in the case of flip chip bonding, which is a more advanced method, small bumps called solder balls are attached to the pad of the chip. Then, the chip is placed onto the substrate, with the top side facing down. In both methods, the assembled unit passes through a tunnel called temperature reflow that can adjust temperature over time to melt the adhesive or solder balls. Then, it is cooled to fix the chip (or bumps) to the substrate.

3. Pick & Place of Chips

Figure 3. Pick & place of a chip

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Individually removing hundreds of chips attached to the dicing tape is called “picking up”. When good chips are picked up from a wafer with a plunger, placing them on the surface of the package substrate is called “placing”. These two tasks called “Pick & Place” are performed on a die bonder¹. After die-bonding all the good chips, unremoved faulty chips remain on the dicing tape, which are all discarded while the frame is recycled. In this process, good chips are sorted by entering the wafer test result (Go / No Go) in the Mapping Table².

4. Chip Ejection

Figure 4. Chip ejection: Enlarged form with the force applied in three directions

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Each chip which has completed the dicing process is individually separated and weakly attached to the dicing tape. At this time, it is not that easy to pick up the chips placed horizontally on the dicing tape one by one. This is because it doesn’t come off easily even when pulled up by using a vacuum, and if pulled out forcibly, it can cause physical damage to the chip.
For this reason, as a method to easily pick up chips, “ejection” is performed in which an ejector³ is used to apply physical force to the target chip to create a slight step difference from other chips. The bottom of the chip is ejected and the chip is pulled up by using a vacuum with a plunger from above. At the same time, the bottom of the dicing tape is pulled with a vacuum to level the wafer.

5. Die Bonding Using Epoxy for Adhesion

When bonding die, an alloy is made by using gold or silver (or nickel), especially for large-sized hermetic packages. It can also be connected by using a solder or a paste containing metal (Power Tr), or polymers (polyimide) are also used for die bonding. Among polymer materials, silver-containing paste-type or liquid-type epoxy is relatively easy to use and is frequently used.

When performing die bonding by using epoxy, a very small amount of epoxy is precisely applied to the substrate by dispensing it. After placing a chip on it, the epoxy is hardened at 150 to 250°C through reflow or curing in order to bond the die and the substrate together. At this time, if the thickness of the applied epoxy is not constant, the warpage that causes bending or distortion can occur due to the difference in the coefficient of thermal expansion. For this reason, while it is more advantageous when the amount of epoxy is less, the warpage occurs in any form as long as epoxy is used.

This is why a more advanced bonding method using a die attach film (DAF) is preferred in recent days. While DAF has some disadvantages of being expensive and difficult to handle, it is easy to apply a certain amount, simplifying the process so that its use is gradually increasing.

6. Die Bonding Using Die Attach Film (DAF)

Figure 6. Die bonding using die attach film (DAF)

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DAF is a film that is attached to the bottom of a die. ▶ Refer to <Singulation, the Moment When a Wafer is Separated into Multiple Semiconductor Chips> With DAF, the thickness can be adjusted to be very thin and constant than when using polymeric materials. It is widely used not only for chip-to-substrate bonding, but also for chip-to-chip bonding to create a multi-chip package (MCP). In other words, the DAF closely bonded to the chip waits for the dicing to be completed and then performs its own function in the die bonding process.

Looking at the structure of the diced chip, the DAF located at the bottom of the chip is holding the chip, and the dicing tape is pulling the DAF under it with weak adhesion. To perform die bonding in this structure, after removing the chip and DAF from the dicing tape at once, the die should be placed on the substrate without using epoxy. Since the dispensing procedure can be skipped in this process, the pros and cons of epoxy are not seen and the pros and cons of DAF newly appear instead.

When using DAFs, some air can penetrate films, causing problems such as deformation of the film. In particular, high precision is required for the equipment that handles DAFs. Nevertheless, using DAFs is the preferred method because it can reduce defect rates and enhance productivity as it simplifies the process and increases uniformity in thickness.

The direction of performing die bonding varies greatly depending on which type of substrate (lead frame or PCB) is based on. PCB-based substrates are used frequently since long ago, as it is possible to mass-produce packages in small sizes. Accordingly, the temperature profile for baking adhesives is also evolving along with the diversification of the bonding technology. Some representative bonding methods include compressing with heat or bonding by using ultrasonic waves. As packages continue to evolve to ultra-thin types with an increased degree of integration, packaging technologies are also diversifying. In the next session, we will cover wire bonding, which is one of these packaging technologies.

¹Die bonder: A device used for die bonding
²Mapping Table: A software that sets the standards of good and faulty chips.
³Ejector: A pin that lifts the chip from under the dicing tape

The post Die Bonding, Process for Placing a Chip on a Package Substrate first appeared on SK hynix Newsroom.

1. Purpose of Back Grinding

Figure 1. The process that changes the form of wafer manufacturing and
semiconductor manufacturing

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In the journey where a wafer is reborn as a semiconductor, the external form continues to change. First, during the wafer manufacturing process, the edge and surface of the wafer are polished. In this process, both sides of a wafer are ground in general. After that, the wafer goes through the front-end process, and then the back grinding, which grinds the back-side only. This is to remove chemically contaminated parts during the front-end process and reduce the thickness of the chip. This is useful for making very thin chips mounted on IC cards or mobile devices. In addition, it has the advantage of reducing resistance, contributing to decreasing power consumption. At the same time, by increasing the thermal conductivity, it can quickly dissipate the heat generated during the normal operation to the back side. Instead, however, as the wafer is thinner, it can be easily broken or warped by external forces, making handling it very difficult.

2. Detailed Processes of Back Grinding

Figure 2. Three detailed processes of back grinding

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Back grinding is divided into three detailed processes. 1) Tape lamination is conducted to attach tape to a wafer. 2) The back side of a wafer is ground. Then, before the sawing process which separates a chip from a wafer, 3) wafer mounting is carried out to place the wafer on the tape. As the third process, wafer mounting is a preparatory step for separating chips (chip saw), it can be included in the sawing process. As the chips are becoming thinner and thinner these days, the order of processes can change sometimes, and each process is subdivided more and more as well.

3. Tape Lamination, a Process for Protecting a Wafer

Figure 3. Tape lamination and wafer structure from the front side

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The first step of back grinding is tape lamination. This is a type of coating, which is a process to attach adhesive tape to the front of a wafer. When conducting back grinding, the silicon compound spreads in all directions, and the wafer can be broken or warped by the grinding force. Especially, as the area of the wafer is larger, it becomes more vulnerable to this phenomenon. For this reason, before the back grinding, a blue thin tape for ultraviolet (UV) should be attached to protect the wafer.

When laminating, increasing the adhesion is necessary so that there are no gaps or bubbles between the wafer and the tape. However, after the back grinding, the tape on the wafer should be detached by irradiating ultraviolet to the surface of the tape to decrease the adhesive strength. After peeling, the residue of the tape shouldn’t remain on the surface of the wafer. Although a tape for non-UV is used sometimes, it has a weak adhesive strength, making it vulnerable to air bubbles. It has a lot of disadvantages, but it is cheap. Also, tapes for bumps which are about twice the thickness of tapes for UV, are applied as well, and it is expected that these will be used more often in the future.

4. Inversely Proportional Relation between Wafer Thickness and Chip Packaging

Figure 4. Multi Chip Package (MCP) structure

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The thickness of a back-ground wafer is reduced from 800-700㎛ to 80-70㎛ in general. Wafers thinned to about a tenth are stacked in four to six layers. Recently, through two grindings, a wafer can be made even thinner to about 20㎛ and it can be stacked up to 16 to 32 layers. This multi-layer structure of semiconductors is called a Multi Chip Package (MCP). In this case, even if it is a structure made with multiple layers, the total height of the finished package should be no more than 1.4mm of thickness, which is the reason why wafers should be ground even thinner. The thinner the wafer is, the more defects occur, making it difficult to proceed to the next process. As a result, advanced technologies are required.

5. Changes in Back Grinding Method

Figure 5. Diversification of grinding method by the thickness of wafers

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Back grinding has been developed by overcoming limitations of processing technology by cutting wafers as thin as possible. A typical wafer with a thickness of 50 μm or more has 3 steps. First, Rough Grinding. Second, Fine Grinding. Through two grindings, the wafers are cut and polished. In this process, we insert slurry and deionized water between the pad and the wafer just like the Chemical Mechanical Polishing (CMP). This abrasive work reduces the friction between wafers and pads, making the surface shine. When the wafer is thick, super fine grinding can be performed, but the thinner the wafer is, the more necessary the grinding is to be carried out.

If a wafer becomes even thinner, external defects occur during the sawing process. For this reason, if the thickness of a wafer is 50㎛ or less, the process order can be changed. In this case, a Dicing before Grinding (DBC) method is used, where sawing for a wafer is performed to half the level, before the first grinding. In the order of dicing, grinding and dicing, chips are separated safely from wafers. Using a sturdy glass plate to protect wafers from breaking is one of the special grinding methods.

As with the growing demand for increased integration due to the miniaturization of electric devices, the back grinding technique should also continue to develop by overcoming its limitations. In other words, it is necessary not only to address the current defects in wafers, but also to prepare for new defects that would occur in the next process. To solve these issues, it is necessary to change the process order or to introduce a chemical etching technique applied to the front-end process to comprehensively develop a new processing method. Many attempts for various changes have been made in the grinding method to solve the problems that might occur in the wafer with the larger area. In addition to this, research on recycling silicon residues after grinding wafers has been being conducted as well.

The post Back Grinding Determines the Thickness of a Wafer first appeared on SK hynix Newsroom.

1. Package Development Flow

Figure 1. Changes in the number of semiconductor packaging pins (or balls)
in contact with the system board

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To develop a new semiconductor package, the way of mounting the package on a system board and the external form of it must be changed. Then, the internal structure and material of the package must also be altered. When a package structure becomes complicated, the more the number of pins or balls in contact with the system board, the less the ball pitch – the distance between balls. The number of contact points between the package and the system board has rapidly approaching its limit and saturation point.

2. Package Structure

Figure 2. Internal and external structure of semiconductor package

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A semiconductor package’s structure consists of a semiconductor chip, a carrier (package PCB, lead frame, etc.) on which the chip is placed, and a molding compound which surrounds them.

In addition, the internal and external connection routes serve to connect signals from internal chips to the outside. Whether it be an internal or external connection, this connection was previously made with lines (wires or lead frames). Recently, however, points (bumpers or balls) are typically being used. Meanwhile, molding compounds play an important role in taking out the heat inside and protecting the chip from external damage.

3. Three Elements Determining Package Types: Internal Structure, External Structure and Mounting

Figure 3. Diagram of package internal connection type, external
connection type and mounting method

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Until the late 1980s, the mainstream package internal connection type was the wire bonding method, which connects the pad on the chip to the pad on the carrier with gold wires. However, as package sizes decreased, the volume occupied by the metal wires within the package increased with it. To solve this problem, instead of removing the metal wires, bumps were used to replace them for internal connections. Of course, that does not mean the wire bonding method became completely unavailable. When bumps are used, it requires the bump attaching process and epoxy under-fill methods instead of the die-attaching and wire bonding processes.

The external connection type has also shifted from the use of lead frames to balls. This is because lead frames have the same disadvantages as wires. While the “wire – lead frame – PCB through-hole mounting” was used before, now the method of “bump – ball grid array (BGA) – surface mounter technology” is the most commonly utilized.

4. Internal Package Type
4.1 Wireless Semiconductor, Flip Chip

Figure 4. Comparison of wire bonding type and flip chip type

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Semiconductor packages can be classified according to internal structure: wiring and flip chip. The wiring method connects the chip and the carrier through wire bonding, with a face up. On the other hand, the flip chip method involves very small diameter balls (a conductive metal called “bump”) being connected to the pad with a face down. In other words, with the flip chip method, the semiconductor chip is in contact with the board without the use of long wires. For this reason, it features a shorter signal travel distance and a more powerful adhesion strength. It is a groundbreaking method in that it addresses the various problems usually associated with wiring.

The greatest advantages of the flip chips are that they reduce the volume of the package and improve the power consumption and signal flow. Due to its shorter length, there are less effect of electrical resistance and noise from the surrounding area, making it faster. Also, what kind of metal a bump is important. Currently, solder or gold is typically used. Deciding what kind of epoxy material to fill the gap between bumps and carrier is another important matter. Besides, since it doesn’t use wires that occupy a large area, the size of the chip after molding can be reduced. This is why it is widely used in small electronic devices like mobile phones. That is, as the footprint area of the package on the system board is reduced, it is applied to high-density board technology. This means a major transformation in the packaging method, with the advent of miniaturized electronic devices such as smartphones.

4.2 TSV (Through Silicon Via), 3D Package Made by Draining Holes in Chips

Figure 5. 3D Package with Via Hole penetrating silicon chips

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We utilize a multi-layered packaging that stacks multiple semiconductor chips to increase the density of the chip package. Multi-chip packaging at the wafer level includes the wire bonding method and Through Silicon Via (TSV). In TSV, once chips are stacked, then you drain holes through them vertically to connect signal lines by using silicon through electrodes. Through this method, the speed of signals is faster and the density of the package can be higher. If the existing method of handling one single chip is regarded as 2D packaging, TSV can be considered 3D packaging. If multi-layered chips are connected with wires, a step-stack structure is formed, increasing the area by about two times. However, in TSV, a direct-stack structure is formed like an apartment building, requiring only around 1.2 times the chip area. TSV, which has excellent area efficiency, is now expanding its application to other fields.

5. External Package Type and Mounting Methods @Based on How the Package Connects to the Outside

Figure 6. Types of external package type and mounting methods

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5.1 External Package Type

Figure 7. IC Package Types

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There are numerous types of packaging chips. As a lead frame type, there is a dipping type suitable for PCB through-hole mounting, which has been developed in the order of SIP1, ZIP2, DIP3, and PGA4. However, since its ability to reduce the footprint area occupying the system board is limited, it is currently used only in some cases.

Meanwhile, among the lead frame types, small outline (SO) is one of surface mounter technologies where the lead is bent to increase the integration. It has been developed to SOIC and SOJ (J type) and is still used widely. In addition to this, a quad flat package (QFP) where the bent leads are applied on four edges is used in CPU chips. After that, the package changed dramatically from the lead frame type to the ball type, presenting a BGA. These days, the ball type is in the more mainstream system.

5.2 Mounting Methods

The package mounting methods are largely divided into surface mounter technology (SMT) and PCB through hole. As the name suggests, SMT fixes a chip to the system board surface via soldering. PCB through hole is a method of cutting a chip’s lead pins into a hole on the system board and then fixing it with soldering

In this method, however, the area occupied by holes on the system board was too large. For light, thin, short, and small packages, the mounting method has also been developed into a surface mounter technology without holes. Among the lead frame methods, SO type (SOIC and SOJ) and TSOP have been developed for surface mounting from the beginning. For the BGA type, it also applies the surface mounting method as well because the ball itself is for mounting on the system board.

Packages have been developing towards “light, thin, short and small packages”. To achieve this, the internal and external shape of the package and mounting methods are changing at the same time. In terms of power, speed, and environment, semiconductor package chips require a high level of performance. They are also transforming in terms of materials to satisfy this. The priority that packages change is usually structure, material, and function in order, but this doesn’t apply to all cases. Package types can be classified as follows: MCP (Multi Chip Package), SiP (System in Package), PoP (Package on Package), CSP (Chip Scale Package), and so on. On this wise, package types can be classified in various ways according to different perspectives. To avoid the confusion that can be caused by this, the structure of the packaged products has become the basis for classification in this chapter.

¹SIP (Single Inline Package): SIP is a package where the pins are arranged in a single row.
²ZIP (Zig-zag Inline Package): ZIP is a package where the pins are arranged in a zig-zag form.
³DIP (Dual Inline Package): DIP is a package where the pins are arranged in two rows.
⁴PGA (Pin Grid Array): PGA is a package with the square or rectangular shape, in which the pins are arranged in a regular array on the underside of the package.

The post “Light, Thin, Short and Small”, The Development of Semiconductor Packages first appeared on SK hynix Newsroom.