A premium, high-performance technology which has revolutionized data processing speeds by vertically stacking multiple DRAMs using through-silicon via (TSV)¹—it is none other than High Bandwidth Memory (HBM). This groundbreaking memory solution utilizes an advanced packaging method to vertically interconnect the upper and lower chips through thousands of microscopic holes in the DRAMs. Through this process, the performance of the HBM product is increased while its size is reduced.

¹Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

As a next-generation memory technology, HBM offers solutions to key problems faced in the memory sector. In the video above, a data bottleneck is demonstrated by the long line of people—representing data—standing at the platform of D (DRAM) Station. So, what causes data to be stuck at a standstill like this?

To provide some context to this issue, it is necessary to know that there are eight DQs², or paths for data input/output, per chip in a typical DRAM. When organized into units of DIMM³ modules, there are a total of 64 DQs. However, as system requirements for DRAMs and processing speed have increased, the amount of data being transferred has risen as well. Consequently, the number of DQs—the number of entrances and exits at D Station—was no longer sufficient for the smooth passage of data.

²DQ: A path for data transfer that acts as the data bus for the communication between the processor and memory. It has the characteristic of being bidirectional as it must be capable of both reading and writing.

³Dual in-line memory module (DIMM): A memory module that is mounted on a printed circuit board and contains multiple memory chips. It is usually used as a primary memory unit in a PC or server.

HBM is the solution for such data bottlenecks. It has a whopping 1,024 DQs and its form factor, which refers to the physical area, is more than 10 times smaller than a standard DRAM thanks to SIP⁴ and TSV technology. As a vast amount of space is required for conventional DRAMs to communicate with processors like CPUs and GPUs since they need to be connected through wire bonding⁵ or PCB traces⁶, it is impossible for DRAMs to conduct parallel processing for large amounts of data. In contrast, HBM products can communicate over very short distances which allows for the increase in DQ paths. These HBM technologies dramatically increase the movement of signals traveling between stacked DRAMs and enable data transfer at high speeds with low power consumption.

⁴System-in-package (SIP): A type of package in which multiple devices are made into a single package to implement a system.

⁵Wire bonding: A method for creating electrical interconnections between electrical device components.

⁶PCB trace: An electrical connection formed on a printed circuit board.

SK hynix, which developed the industry’s first HBM in 2013, began mass production of HBM3 in June 2022. As the fourth generation of HBM, HBM3 is approximately 78% faster than its predecessor, HBM2E. With such capabilities, HBM products can be deployed in high-performance data centers and applied to machine learning, supercomputers, artificial intelligence systems, and other advanced technologies.

SK hynix will continue to develop HBM products while ensuring that all its solutions adhere to ESG management standards to maintain its position as a leader in the premium memory market.

<Other articles from this series>
[We Do Future Technology] Become a Semiconductor Expert with SK hynix – AI Semiconductors

[We Do Future Technology] Become a Semiconductor Expert with SK hynix – UFS

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SK hynix announced HBM3’s development in October 2021, with the company beginning to mass produce the product in June 2022. SK hynix will also provide HBM3 for NVIDIA systems that are expected to begin shipping in the third quarter of 2022.

How did the company maintain its leadership position in this market, and what lessons did it implement from developing the previous generations of HBM products?

HBM1 – First Mover from the Get-go

When HBM was developed as a memory solution optimized for high-level computing performance (HCP), it offered a new paradigm on solving the memory bottleneck as it aimed to increase capacity and bandwidth simultaneously. SK hynix jointly developed the world’s first TSV (Through Silicon Via) HBM product with AMD in 2014. The two companies also teamed up to develop high-bandwidth 3-D stacked memory technologies and related products.

HBM1’s operating frequency is around 1,600 Mbps, the VDD (drain power voltage) is 1.2V, and the die density is 2Gb (4-hi). The product had a higher bandwidth than the DDR4 and GDDR5 products, while using less power in a substantially smaller form factor, benefitting bandwidth-hungry processors such as GPUs (graphics processing units).

HBM2 – Second Generation Home Improvements

In the second generation HBM2, released in 2018, a key improvement was the Pseudo Channel mode.  This mode divides a channel into two separate 64-bit I/O sub-channels, as well as providing 128-bit prefetch per memory read and write access for each sub-channel. The mode optimizes memory accesses and lowers latency, resulting in higher effective bandwidth.

Other improvements included lane remapping modes for both hard and soft repairs of lanes, as well as anti-overheating protection. The newer technologies, alongside HBM2’s higher effective bandwidth, give it a higher energy efficiency than HBM1 at its data-rate.

HBM2E – Round Three Game Changer

SK hynix was also the first memory vendor to begin mass producing HBM2E, an extended version of HBM2. The HBM2E development team’s determination to raise the product’s specifications at the planning stage played a critical role in helping SK hynix to maintain its leadership position. The product was released two years after HBM2 in 2020, with technological updates and more applications, as well as a faster speed and higher capacity than HBM2.

The product’s 16Gb die density was double that of HBM2, achieved by vertically stacking eight 16Gb chips via TSV technology. At the time of its release, HBM2E had the industry’s fastest memory at 3.6Gbps in I/O speed and processing 460GB of data per second using 1,024 I/Os. HBM2E also has 36% better heat dissipation than HBM2.

HBM3 – Maintaining Leadership into the Fourth Generation

SK hynix continued maintaining its leadership status with HBM3, which was the world’s first of its kind when the company developed it in 2021. HBM3 has 1.5 times HBM2E’s capacity from 12 DRAM die stacked to the same total package height, enabling it to power capacity-intensive applications such as AI and HPC.

A significant addition in HBM3 compared to previous generations is a custom-designed on-die ECC (Error Correcting Code), which uses pre-allocated parity bits to check and correct errors in the data received. The code also allows DRAM to self-correct errors within cells, enhancing device reliability.

HBM3’s 16-channel architecture runs at 6.4Gbps, double that of HBM2E and currently the fastest in the world. This makes HBM3 and other HBM products an indispensable component of digital life, such as HBM products becoming a prerequisite for the Levels 4 and 5 of driving automation in autonomous vehicles.

SK hynix’s HBM development is also an important component of the company’s ESG efforts, with each generation of the product designed to consume less power than the previous one. For example, HBM3 runs at lower temperatures than HBM2E at the same level of operating voltage, enhancing the stability of the server system environment, and increasing cooling capacity.

After celebrating its HBM3 achievements, the development team has already moved onto the next step, cooperating with clients, and receiving feedback on the product. Predictions are also already out for HBM4, which could be more widely used in areas such as high-performance data centers, super computers, and artificial intelligence.

The HBM market also continues its steady growth, with the volume of data transmission increasing rapidly in the 5G era and a 2021 report by Omdia predicting that the market will generate $2.5 billion in revenue by 2025. SK hynix is looking to secure its leadership in the market by continuing to take its HBM products to the next level and maintaining its position as not only a “first mover”, but also a “solution provider”.

The post Continuing to Make HBM History: The Story of SK hynix’s HBM Development first appeared on SK hynix Newsroom.

As part of the Intel® ON Series, Intel Vision is a newly envisioned ICT conference and exhibition being held this year for the first time. Decision makers from major players in the technology field, as well as renowned industry opinion leaders, were invited to the event featuring the latest innovations and technologies from Intel and its partners. 

Image 1. View of SK hynix’s booth at Intel Vision

SK hynix is a key player in the memory field and has a long-standing partnership with Intel. The solid relationship was on full display at the hybrid online and offline event where SK hynix was an invited guest. 

At its booth, SK hynix presented its DDR5¹⁾DRAM, developed in October 2020 as the first of its kind in the world.
The company continued its dominance as a leader in DRAM technology by releasing the industry’s largest density 24 Gb (gigabit) DDR5 product sample in December 2021. 

DDR5 allows for high-speed processes with bandwidth speeds at least 50% faster than DDR4 and can support 256 GB of high density using TSV technology. It also proves more trustworthy by self-correcting errors in units of 1 bit with a built-in Error Correcting Code (ECC). Systems using SK hynix’s DDR5 are expected to see reliability improve by roughly 20 times. 

Image 2. SK hynix’s latest memory solutions facing server applications presented at Intel Vision

These features allow for more stable and seamless usage in big data processes like cloud computing, artificial intelligence (AI), and machine learning (ML), as well as the metaverse. 

It’s also the most environmentally beneficial DDR product to date with a low operating voltage of 1.1 V, reducing electricity consumption by 20%. Along with the premium memory HBM3²⁾, these products will continue to carry the load from a total cost of ownership (TCO) standpoint. 

SK hynix also introduced its GDDR6-AiM, the latest PiM³⁾ solution at SK hynix, and Compute Express Link (CXL) capabilities. 

GDDR6-AiM was first unveiled at 2022 ISSCC⁴⁾ in San Francisco in early 2022. It allows for computational functions to be added to memory chips. When combined with CPU/GPU, GDDR6-AiM can improve the overall processing speeds by up to 16 times. The next–generation intelligent memory chip can be used where fast computations are needed, like machine learning and high–performance computing (HPC). It reduces power consumption in the CPU/GPU by reducing data transfer, thereby lowering energy usage by approximately 80% compared to previous products. That in turn is expected to make it more effective in lowering carbon emissions. 

CXL⁵⁾ is a new, up-and-coming interface solution that is expected to contribute to expanded memory performance and enhanced speeds. 

“Participating at Intel Vision further solidified our partnership with Intel,” said Sungsoo Ryu, Head of DRAM Product Planning & Enabling at SK hynix. “SK hynix plans to continue to strengthen its competitiveness in providing total memory solutions from datacenter memory, like DDR5 and CXL memory, to memory solutions facing client devices.” 

Image 3. Miniature of M16 Fab at SK hynix Icheon Campus

By participating in the Intel Vision event, SK hynix raised expectations for future endeavors by further committing to R&D in the memory industry and solidifying its cooperation and partnership with Intel. 

¹DDR (Double Data Rate): DRAM standard specification defined by the Joint Electron Device Engineering Council (JEDEC). DDR5 is the next-generation DRAM standard set to replace the current DDR4.
²HBM (High Bandwidth Memory): Following previous generations of HBM, HBM2, and HBM2E, HBM3 is an upgrade to HBM2 specifications with increased bandwidth and capacities.
³PiM (Processing in Memory): Next-generation technology that provides a solution for data congestion issues for AI and big data by adding computational functions to semiconductor memory.
⁴ISSCC: The International Solid-State Circuits Conference was held virtually from February 20-24, 2022, under the theme, “Intelligent Silicon for a Sustainable World.”
⁵CXL (Compute Express Link) Memory: Heterogeneous computing memory interface that is different from existing DDRx interface. CXL interface can realize memories such as bandwidth & capacity expansion memory, persistent memory, and pooled memory. Major players in datacenter industry ecosystem are currently participating in the CXL consortium.

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SK hynix Inc. (or ‘the Company’, www.skhynix.com) today announced that it has shipped samples of 24 Gigabit (Gb) DDR5* DRAM with the industry’s largest density for a single DRAM chip.

* DDR (Double Data Rate): A comprehensive standard specification defined by JEDEC (Joint Electron Device Engineering Council) and applied to PCs, servers and other applications; currently includes 5 generations of DDR 1-2-3-4-5

** Currently, DDR DRAM offerings mostly come in density of 8Gb or 16Gb, with the highest density of 16Gb

The announcement of SK hynix releasing the industry’s largest density DDR5 chip comes in just 14 months after the Company became the first to release DDR5 DRAM in October 2020, further solidifying the chipmaker’s technological leadership in DDR5.

The new 24Gb DDR5 was produced with the cutting-edge 1anm technology that utilizes EUV process. It has a density of 24Gb per chip, which is up from the existing density of 16Gb in 1ynm DDR5, with improved production efficiency and increased speed by up to 33%.

In addition, SK hynix managed to reduce the product’s power consumption by *25% compared to existing products while lowering energy use in manufacturing through enhanced production efficiency. SK hynix expects the product to bring about reduction in carbon emissions as well, which is meaningful in the context of ESG management.

*Based on system power consumption to support the same module capacity

The initial offerings on this product are set to be 48 Gigabyte (GB) and 96GB modules for supply to cloud data centers. It is also expected to power high-performance servers for big data processing such as artificial intelligence (AI) and machine learning, as well as realizing Metaverse applications among others.

Kevin (Jongwon) Noh, President and Chief Marketing Officer at SK hynix, said, “In line with the release of 24Gb DDR5, SK hynix is closely engaging with a number of customers that provides cloud services. We will continue to strengthen our leadership in growing DDR5 market by introducing advanced technologies and developing products with ESG-awareness.”

“Intel and SK hynix have a long history of strong collaboration,” said Carolyn Duran, Vice President of Memory and IO Technologies in Intel’s Data Center and AI Group. “Today’s announcement is another illustration of our two companies working together to deliver a 24Gb solution to address needs of our mutual customers. The 24Gb DDR5 offering provides high mono die capacity and will help customers boost performance of memory capacity bound workloads such as data analytics while bringing significant TCO benefits.”

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About SK hynix Inc.

SK hynix Inc., headquartered in Korea, is the world’s top tier semiconductor supplier offering Dynamic Random Access Memory chips (“DRAM”), flash memory chips (“NAND flash”) and CMOS Image Sensors (“CIS”) for a wide range of distinguished customers globally. The Company’s shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxemburg Stock Exchange. Further information about SK hynix is available at www.skhynix.com, news.skhynix.com.

Media Contact

SK hynix Inc.
Global Public Relations

Technical Leader
Jaehwan Kevin Kim
E-Mail: global_newsroom@skhynix.com

Technical Leader
Kanga Kong
E-Mail: global_newsroom@skhynix.com

Technical Leader
Eun Suk Yixi Lee
E-Mail: global_newsroom@skhynix.com

The post SK hynix becomes the Industry’s First to Ship 24Gb DDR5 Samples first appeared on SK hynix Newsroom.

SK hynix Inc. (or “the Company”, www.skhynix.com) announced that it has become the first in the industry to successfully develop the High Bandwidth Memory 3, the world’s best-performing DRAM.

HBM3, the fourth generation of the HBM technology* with a combination of multiple DRAM chips vertically connected, is a high value product that innovatively raises the data processing rate.

*Previous three generations are HBM, HBM2 and HBM2E, which is an update to the HBM2 specification with increased bandwidth and capacities.

The latest development, which follows the start of mass production of HBM2E in July last year, is expected to help consolidate the company’s leadership in the market. SK hynix was also the first in the industry to start mass production of HBM2E.

SK hynix’s HBM3 is not only the fastest DRAM in the world, but also comes with the biggest capacity and significantly improved level of quality.

The latest product can process up to 819GB (Gigabyte) per second, meaning that 163 FHD (full-HD) movies (5GB each) can be transmitted in a single second. This represents a 78% increase in the data-processing speed compared with the HBM2E.

It also corrects data (bit) errors with the help of the built-in on-die error-correction code, significantly improving the reliability of the product.

SK hynix’s HBM3 will be provided in two capacity types of 24GB – the industry’s biggest — and 16GB. For the 24GB product, SK hynix engineers ground the height of a DRAM chip to approximately 30 micrometer (μm, 10-6m), equivalent to a third of an A4 paper’s thickness, before vertically stacking 12 chips using the through silicon via technology.

*Through Silicon Via (TSV): An interconnecting technology that links the upper and lower chips with electrode that vertically passes through thousands of fine holes on DRAM chips

HBM3 is expected to be mainly adopted by high-performance data centers as well as machine learning platforms that enhance the level of artificial intelligence and super computing performance used to conduct climate change analysis and drug development.

“Since its launch of the world’s first HBM DRAM, SK hynix has succeeded in developing the industry’s first HBM3 after leading the HBM2E market,” said Seon-yong Cha, Executive Vice President in charge of the DRAM development. “We will continue our efforts to solidify our leadership in the premium memory market and help boost the values of our customers by providing products that are in line with the ESG management standards.”

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About SK hynix Inc.

SK hynix Inc., headquartered in Korea, is the world’s top tier semiconductor supplier offering Dynamic Random Access Memory chips (“DRAM”), flash memory chips (“NAND flash”) and CMOS Image Sensors (“CIS”) for a wide range of distinguished customers globally. The Company’s shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxemburg Stock Exchange. Further information about SK hynix is available at www.skhynix.com, news.skhynix.com.

Media Contact

SK hynix Inc.
Global Public Relations

Technical Leader
Jaehwan Kevin Kim
E-Mail: global_newsroom@skhynix.com

Technical Leader
Kanga Kong
E-Mail: global_newsroom@skhynix.com

Technical Leader
Eun Suk Yixi Lee
E-Mail: global_newsroom@skhynix.com

The post SK hynix Announces Development of HBM3 DRAM first appeared on SK hynix Newsroom.

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The semiconductor industry enables and supports all aspects of modern life. Semiconductor products provide the processing for data centers, the network edge and in embedded industrial and consumer devices. It also provides fast network communication required for data centers and connected devices. Semiconductor memory/storage products such as DRAM and NAND flash provide the memory and long-term storage of information required to support data processing and to keep the results of that processing available for future access.

Vehicles are becoming mobile computers with semiconductors ensuring efficient operation, ADAS and autonomous driving services as well as infotainment. Embedded connected electronics control factory operations and enable smart cities. They are an essential element in Internet of Things (IoT) applications, including wearable devices that help us stay connected and provide ways to monitor our health and motivate us to stay healthy.

Let’s take a look at how the semiconductor industry works, the impact of the COVID-19 pandemic on the industry and how the increasing capabilities of semiconductor devices will enable an amazing array of products and services that will allow us to work more effectively, manufacture products more efficiently, keep us healthier and entertain us in more engaging and immersive ways.

Big Breakthroughs for Smaller Tech

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The semiconductor industry creates small electronic devices (chips) that can be incorporated into various products. These chips use electric energy to process data, control operations, encrypt and decrypt data and store data temporarily or long term.

Semiconductors are made on mostly silicon wafers in large factories and using sophisticated and expensive equipment. For instance, a modern 3D NAND flash fab costs more than $10B to equip and build, and if it is a brand-new plant, may take a year and a half to come online with high production volumes. The equipment required for a semiconductor fab depends upon what sort of wafers are being processed.

Some semiconductor companies, such as SK hynix, make all or most of their own wafers and chips. Many other semiconductor companies own no semiconductor fabs and instead have their chips manufactured in large semiconductor foundries. These companies are called fabless semiconductor companies. There are several large semiconductor foundry companies in various parts of the world that service these fabless companies.

Semiconductor development is following what has been known as Moore’s Law, named after Gordon Moore, one of the founders of Intel. This “law”, which is a projection of a historical trend first observed in the 1960’s, said that the number of transistors on semiconductor integrated circuits (ICs or chips) doubles about every two years. This doubling of circuit density was accompanied by various other scaling trends, increasing the performance and lowering the power required by the ICs as well.

Moore’s Law has become more difficult to sustain in recent years as the size of the features that make up a transistor have shrunk. The equipment to manufacture these small features has also increased significantly in price. Currently semiconductor devices are available in volume at down to 7nm minimum feature sizes with 5nm planned and work underway for 2nm and less.

But, because of the cost to make these small features, new ways to design chips have emerged. For instance, some companies are breaking up the capabilities that might have been built into a single chip using one lithographic node into multiple chips with different minimum lithographic feature requirements, called chiplets. These chiplets are located next to each other in a chip module. Another approach is to stack and connect wafers on top of each other that may differ in their lithographic processes and even their particular operations (e.g. CPUs, memory and specialized processing for particular tasks).

With these new approaches for semiconductor devices, chips with larger lithographic features can be used for many functions, focusing the more expensive small features processes where they do the most good and avoiding the expense of converting all the semiconductor operations to the smaller lithographic node.

The Pandemic-Induced Shortage Felt Around the World

With the COVID-19 pandemic in 2020, many semiconductor fabs went idle for a time and the semiconductor supply chain was temporarily disrupted. At the same time global demand for mobile devices, PCs and data center equipment surged in response to online learning, remote work and other activities.

Also, during the pandemic, some industries, such as the automotive industry, cut back on their orders for chips, anticipating weaker demand. Semiconductor companies responded by allocating more output to semiconductors for other applications. As the pandemic has eased with the introduction of vaccines, demand for products such as automobiles has increased, but many semiconductor companies don’t have additional capacity to meet this demand. Because of the time it takes to bring new semiconductor capacity online, several semiconductor companies have said that it could take a couple of years for capacity to meet demand.

Leveraging New Technologies, Broadening Markets

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In addition to semiconductor shortages for products like automobiles, the overall demand for semiconductors is increasing to provide advanced cloud services, wireless networks (such as 5G and WiFi6) and to support the application of artificial intelligence (AI) at the network edge and in industrial, civic and consumer endpoint devices.

5G smartphones may use $25 worth of chips compared to $18 in 4G and $8 in 3G phones. Nearly three-quarters of all cars will likely ship with cellular connectivity by 2024 and the cost of electronic components in cars was about 45% of the total car cost in 2020, up from 20% in 2000¹.

Semiconductors and wireless connectivity are enabling new wearable and embedded devices that will help us stay healthy. They will also power a new generation of robots used in human/robot manufacturing teams and for home health care and companionship.

In addition to computing, communication, healthcare and transportation, entertainment systems use lots of chips. With the introduction of high dynamic range 8K video, virtual and augmented reality and even more advanced immersive audio-video technologies, demand for semiconductors to produce, process and deliver this content will soar.

Semiconductors will help the unconnected have access to the Internet and a better life, create safer transportation and cities, make our factories more efficient, keep us healthier and entertain and educate us in new ways.

¹https://www.fool.com/investing/2021/04/27/6-causes-of-the-global-semiconductor-shortage/

The post Global Trends, Semiconductors, and Evolving Market Demands first appeared on SK hynix Newsroom.

You would think that if density is high, storage capacity will be enhanced, and therefore, the semiconductor to be more expensive. But the price of a semiconductor memory chip is not proportional to its density. In fact, it is unrelated to density, or fluctuates inversely to density in the range of one US dollar to eight US dollars. Around 40 leading companies around the world that failed to adapt fell behind. And only three to four companies that manufactures DRAM and NAND, respectively, survived, enjoying the global market for the past decade.

Then, what correlation is there between memory density and the cost of semiconductor products? And what impact does these factors have on the memory semiconductor market?

1. The law of increasing semiconductor memory density, about 1,000 times (2¹⁰) a decade

Figure 1. Yearly comparison of density increase trends between DRAM and NAND

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The density of semiconductor memories began with 1Kbit DRAM in the 1970s and showed a trend of increasing by about 1,000 times (2¹⁰) in every 10 years. The 1980s was the age of the megabit and the 1990s and the 2000s were a time when the megabit increased to the gigabit.

However, the true winner of actual density in memory was NAND, which appeared in early 2000. At first, in the initial stages of NAND, SLC products of less than 1Gbit in capacity, or 128Mbit (Mega: 2²⁰) and 256Mbit, appeared in the market. After a decade, MLC products of about 1,000 times the capacity, or 64Gbit (Giga: 2³⁰) and 128Gbit, became the mainstream. Recently, in the early 2020s, TLC products of terabit (2⁴⁰), which is 1,000 times the Gbit, started to become the mainstream product.

This shows a trend of NAND density increasing by around 1,000 times over 10 to 15 years. With this trend, the era of the petabit (2⁵⁰) (QLC-NAND), which is 1,000 times the terabit, will come in the early 2030s. One book takes up less than 10Mbit and a movie at around 20Gbit, meaning that 1Tbit will allow you to save more than 100,000 books you will read in a lifetime or dozens of movies.

For DRAM, 64Gbit to 128Gbit products (DDR5) have been released recently, maintaining a density of 1/100 times the density of NAND in 2020. It is expected that this gap will widen over time, showing a 1,000-fold gap in 2030 and more than a 10,000-fold gap in 2040.

2. Maximizing density and minimizing chip surface area → Leading prices

Figure 2. Pricing structure of semiconductors

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Suppliers focus on increasing density per chip or the number of chips in a wafer to the maximum to lower the sales price or unit cost of semiconductors. The purpose of increasing density per chip is not only because of the demand for storing as much data as possible in the chip, but also because customers continuously seek a continuous cost down in semiconductors. On the other hand, the reason for increasing the number of chips in a wafer, or Net Die, is because the supplier wishes to achieve cost saving regardless of the demand of the market. In other words, higher specification in density is in line with the common interest of both suppliers and demanders, while the increase in the number of chips or net die purely contributes to the supplier’s profits.

Here, the supplier increases density per chip and net die per wafer to satisfy both needs (high density, cost saving) at the same time, while additionally lowers its profits. This is due to the semiconductor ‘chicken game,’ trying to overwhelm competitors in the market by adopting a strategy of lowering profitability, but increasing market share instead. In this case, the supplier must create an environment where it gains profit, but its competitors lose. This is only possible when there is a significant gap between the supplier’s cost and its competitors’ cost.

A supplier that wins in the cost competition can gain a dominant position in pricing and therefore, suppliers mobilize all capabilities, including technology and sales condition, and pursue a low-cost policy to increase global market share. If this continues, competitors will fail to improve profit structure and inevitably be thrown out of the market. For example, the former global DRAM semiconductor company Elpida Memory and German company Infineon lost in the chicken game and sold its DRAM business or withdrew from the market despite many efforts made at the national level to revive the companies.

2-1. Maximizing density → Forming low cost per production of bit

Figure 3. Lowering production cost of bit by increasing chip density @ chip price set arbitrarily

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Typically, increasing density is about planning a new product, designing based on device technology, and completing its features and reliability accordingly. To increase density, you need to either increase the number of cells physically even if it leads to a slightly larger chip size or increase the number of bits electronically. In semiconductors, physical cells refer to transistors (TR) and therefore, one must make TR smaller or minimize the width of circuit lines that connect TRs. These are some examples of conventional scaling down in semiconductor memories and can be applied to all memories, including DRAM and NAND.

Manufacturing by only increasing the number of bits is a method that differentiates based on the level of storage capacity of electrons within the cells of a certain size. This is not a physical method and therefore has no relevance with the size of TR or circuit linewidth. Increasing number of bits within the physical cell is only an option applicable to NAND. Currently, major NAND products can store three bits of information per cell (triple-level-cell, TLC). DRAM, which stores 1 bit per cell, must lower the cost per bit through physical methods, while 3 bits-per-cell NAND has the upper hand being able to use both physical and electronical methods. Therefore, the leading role in the development of memory density has transferred from DRAM to NAND. For various reasons, DRAM costs more than 10 times NAND in terms of cost per bit.

When the density of a product is increased, the price of the product goes up as well. The incremental price increase, however, is smaller than the incremental density increase. So, even if the price goes up by 1.5 times, the density mostly increases by 4 times (2 to 4 times), meaning that demanders enjoy a gain of more than 2.5-fold. In other words, even if a new semiconductor product is offered at a high price, the density increases more than the incremental price increase, making it beneficial to demanders, while also creating a favorable structure for suppliers by forming a lower price per bit. However, in reality, density increase leads to larger chip size along with other variables. And the launch price, unlike during the planning phase, may vary according to market variables such as the timing of the release.

2-2. Minimizing chip size → Forming low cost per production of chip

Figure 4. Lowering cost per chip by increasing number of chips per wafer
@ number of chips and price set arbitrarily

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Increasing the number of chips per wafer requires minimizing the surface area of chips physically. This requires reducing the width of circuit lines or maximizing cell efficiency to reduce chip size. But narrowing the linewidth of circuits makes the reliability and function of device (TR) vulnerable. Therefore, the design rule is to find the optimal design requirement to increase the number of chips because there is a limit to making cell size smaller.

The design rule, in the narrow sense, refers to the layout of the optimal conditions for conductor linewidth and the physical space between conductor lines, while ensuring the electrical characteristics of the design. However, in the broader sense, design rule refers to setting up the optimal conditions for various factors, including process state, physical form of package, and permitted electrical condition. Maximizing number of chips per wafer can increase the price of wafer per sheet which ultimately helps suppliers reduce cost per chip.

3. The rise and fall of IDM companies

Figure 5. Yearly changes in the number of global DRAM IDM companies
@ excluding companies with less than 3% market share in global DRAM market

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Starting with Intel in 1970, the semiconductor memory business was considered as a profitable business. About 20 American electronic companies entered the business, making it a US-led industry. In the 1980s, around 10 global electronic companies in Japan led by Hitachi also entered the market, creating a booming semiconductor industry. Since then, the semiconductor craze spread to Korea, establishing a 3-pillar structure among Samsung Electronics, SK hynix (former Hyundai Electronics), and LG Semiconductor. Semiconductor also became a good business to almost 10 ITC companies in Europe, including SGS-Thomson Microelectronics. As a result, about 40 companies entered the market from the 1970s to 1990s, but around 10 companies disappeared every decade due to cost-saving war. After two fierce chicken games in the industry, companies that were once outstanding with great technological prowess disappeared from the market. And currently, three DRAM IDM companies (Samsung Electronics, SK hynix, and Micron) and four NAND IDM companies (Samsung Electronics, SK hynix, Kioxia (former Toshiba), and Micron) are solidifying their status and position.

There are several options other than what have been introduced today in increasing density and lowering cost. Measures, including evolving from 2D to 3D, applying EUV and new processing methods, increasing number of bits per cell (NAND), TSV (DRAM) and structural improvements like 4D, are made in multifaceted approach. It is expected that PCRAM, MRAM, ReRAM and other types of new products based on the concept of NAND will contribute as next-generation memories. The strategy of balancing product pricing through cost saving can appear anytime in the demander-favorable market, while suppliers can also take the challenging environment as an opportunity to surpass competitors significantly.

The post The Density, Cost, and Marketing of Semiconductor Memory first appeared on SK hynix Newsroom.

As the automotive industry continues to develop beyond the concept of traditional cars, the industry is entering a revolutionary period. Future mobility is quickly approaching on the horizon, and with the introduction of Advanced Driver Assistance System (ADAS), In-Vehicle Infotainment (IVI), multi-camera vision processing and self-driving cars, ultra-huge computing processing has become a necessity.

19th-century internal combustion engines combined with 20th-century electrical systems have paved the way for the automotive technology of the 21st-century, which is now undergoing a massive digital transformation. Cars today, and tomorrow, will be more Connected, Autonomous, Shared and Electric than ever before, which is why this transformation has been dubbed the ‘CASE Revolution.’

The CASE Revolution is characterized by complex and efficient interconnectivity as well as integrated systems inside and outside of the vehicle. Enabled by the advancement of automotive electronics, trends like the increased adoption of infotainment systems, long-life batteries and ultrafast 5G networks all require high-capacity memory. Consequently, they are driving massive demand for DRAM and NAND solutions in the global automotive market.

The Next Generation of Automobile Memory

The surge in electric vehicles (EV) and hybrid vehicles, accompanied by the emergence of ADAS, Graphic Instrument Cluster (GIC), infotainment systems and fully autonomous driving solutions has created a need for Electronic Control Units (ECU) – automotive computer controllers used to receive and process signals from sensors and export control commands to the actuator to execute.

In traditional automotive Electrical / Electronic (E/E) modular architecture, each distributed ECU handles a single function independently. As modern vehicles contain many electronic functions, the number of ECUs increases dramatically from low/mid-end cars (around 30) for high-end cars (around 100). As a result, integrated ECU controllers like vehicle integration platforms and functional centralization have been introduced as a way to reduce cost and maximize power efficiency in four main areas: Powertrain, ADAS, Body, and IVI.

Figure 1. The diagrams of Distributed ECU, Integrated ECU, and DCU

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As the autonomous driving level evolves and the variety of IVI contents diversifies, the amount of data being processed has increased tremendously – this is a result of simultaneous complex cross functions and a connected network. Consolidation of ECUs into DCUs (Domain Control Units) reduces cost, weight and power consumption. DCU is a highly integrated domain control unit that implements advanced competencies like multi-sensor fusion and 3D localization. For example, vision processing for Level 4~5 Autonomous driving capabilities can contain up to 12 cameras with resolution up to 8M pixels, 60 Frame/sec refresh rates, and 16bit depth, allowing the data streaming rate to reach almost 10 GB/s.

Figure 2. Storage in a Modern Car¹

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Automotive LPDDR4 and LPDDR5 were originally designed for mobile applications, however, they’re being supercharged to meet auto-grade qualifications that are more demanding than for mobile applications. The LPDDR5 in particular has been adapted for much bigger displays in the latest vehicles to manage increasingly sophisticated navigational images and the control area of cockpit units. Furthermore, the digital cluster, front & rear sensors, and driver monitoring system utilizing in-cabin cameras, which are derived from traditional IVI, all require LPDDR5 DRAM’s high-end functionality.

However, higher computing and communication performance requires more electrical power demand – at least up to 4 kW. As tightening CO2-emission regulations for internal combustion engines (ICE) and range requirements for Battery Electric Vehicles (BEV) limit the overall power consumption, future E/E architectures and automotive memory must become more energy efficient. The next generation of automobile memory needs to push the envelope in bandwidth, latency, power, and capacity.

High-capacity NAND Flash memory modules also play an important role in many automotive applications and systems. When accidents happen, it is extremely important to capture the data of certain sensors in real-time and store it permanently in memory. Similarly, ADAS should draw the driver’s attention to potential dangers – like cars or other obstacles being too close. Adaptive functions can automatically switch on the headlights, regulate driving speed, initiate emergency braking, alert the driver to surrounding vehicles, keep the vehicle in its lane and even monitor a driver’s “blind spot.” Furthermore, the settings of the infotainment system must be instantaneously stored so that they are not lost in the event of a power failure. Both GIC and infotainment systems work with high-quality graphics and therefore require large amounts of overlay data. All these functions use non-volatile memory.

Figure 3. Estimated Density and Storage Type of NAND Flash Memory for Each Application

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[SK hynix’s Efforts in Automotive Semiconductor Industry]

Increasingly, automakers and semiconductor companies are joining forces as the auto industry progresses rapidly from merely adding electronics to actually building self-driving vehicles. While it grows with the industry, automotive memory must also continue to maintain the highest safety protection and superior quality. Making significant strides in the automotive semiconductor market in 2020, SK hynix is relentlessly pursuing the best performance and the highest quality.

To provide this, SK hynix is committed to supporting AEC-Q100² and building up its standard process – from designing in the R&D stage to manufacturing following IATF 16949³. There is also another standard called Automotive Software Performance Improvement and Capability Determination (ASPICE⁴), which is an established framework for measuring process quality. Functional safety (ISO 26262⁵) is another important aspect of safety-critical applications. SK hynix is working hard to meet all these standards, and only when we have achieved them can our products obtain the certifications and qualifications required in the automotive sector.

These automotive industry standards help ensure clear communication among stakeholders throughout the product lifecycle. The traceability not only helps product designers, engineers and testers develop with confidence, it also makes the market safer, and vehicles more reliable. Adhering to these standards will lead to better quality, higher efficiency, and lower failure rates.

SK hynix’s automotive memory is enabling technology for the development of ECC⁶ (Error Correction Code), BIST⁷ (Built-In Self-Test), and CRC⁸ (Cyclic Redundancy Check), and SK hynix is also creating a bit-cell that is more temperature resistant and introduces error correction within DRAM die that have lost their charge between refreshes. SK hynix is even applying the error correction function not only within the DRAM die but also in the DRAM interface to mitigate possible errors in automotive memory.

For NAND Flash, SK hynix applied TLC (Triple-Level-Cell) 4D NAND with PUC (Peri. Under Cell) technology to automotive UFS to guarantee its high-performance. It boasts faster random write and read speeds than eMMC 5.1 interface, enhancing the performance of IVI systems and instrument clusters. Automotive UFS is a high-performance storage interface ideal for advanced automotive systems that need ultra-fast boot capability and automotive-grade reliability.

Figure 4. SK Mobility Technology

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Figure 5. 8Gb LPDDR4 with 20nm Technology

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In conjunction with other SK Group affiliates, such as SK Telecom, SK Innovation, and others, SK hynix will lead the e-mobility industry’s revolution and contribute to the creation of both economic and social value with advanced and environmentally friendly semiconductor technologies.

SK hynix’s advanced, high-quality automotive memory products will push forward a new e-mobility era and deliver superior convenience to drivers around the world.

¹Presentation material “Infotainment and Autonomous Vehicles – The challenges of storage” by Michael Huonker, Daimler AG Research & Development, at FMS 2019
²AEC (Automotive Electronics Council): AEC-Q100 is a Failure Mechanism Based Stress Test Qualification for Integrated Circuits
³IATF (International Automotive Task Force): IATF 16949 is an Essential certification to improve automotive quality management systems that meet the specific needs of the customer
⁴Source: Automotive Spice (http://www.automotivespice.com/)
⁵ISO 26262: An international standard for functional safety of electrical and/or electronic systems in production automobiles defined by the International Organization for Standardization (ISO) in 2011
⁶ECC (Error Correction Code): Method for controlling errors in data over unreliable or noisy communication channels
⁷BIST (Built-In Self-Test): Mechanism that permits a machine to test itself for high reliability and lower repair cycle times
⁸CRC (Cycle Redundancy Check): An Error-detecting code to detect accidental changes to raw data

The post A Look at Automotive Memory in the E-Mobility Era first appeared on SK hynix Newsroom.

The demand for mobile memory is steadily enhancing along with the consistent growth of mobile and wearable devices. When it comes to mobile devices, portability is pretty much everything which is why low-power and ultra-thin PKG technology has established itself as an essential element for the semiconductor industry.

Inline Re-distribution Layer (IRDL) technology is an advanced FAB technology that forms wiring by using an extra metal layer with an insulation layer and aluminum, enabling IO pads to relocate freely to the PKG wire bonding position where necessary. This technology allows you to make chip-to-chip bonding thinner and simpler. Additionally, IRDL, one of RDL technologies, was named so as the entire process takes place inside a FAB, unlike PKG RDL.
The figures below show the two MCP¹ methods for chips. “Vertical-Stack MCP” (left) is the existing technique where upper chips stack vertically on the lower chips’ bonding pad. “Shift-Stack MCP using RDL,” (right) on the other hand uses a shift-stacked method by avoiding the bonding pad. This way, wire interference and short from wire to chip that could occur within the vertical-stack MCP can be prevented. The gap between the upper chip and the lower chip reduces when this new method is applied, making it significantly easier to meet the proper thickness that the customers require.

Figure 1. Vertical-Stack MCP vs Shift-Stack MCP

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Figure 2. Cross-Sectional View of Figure 1

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Comparing existing PKG RDL and IRDL processes

The major difference between PKG RDL and IRDL lies within the structure formation method, so let’s learn more about the benefits of IRDL.

PKG RDL’s structure formation method is largely divided into two processes: FAB-in and FAB-out. The FAB-in process involves covering a top metal by an insulating material with only pads open. Then, in the FAB-out process, you apply the 1st dielectric layer to separate the RDL line from the insulating materials on top of the wafer, and form lines using gold. After that, a 2nd dielectric layer is applied to cover the top of the line.

On the other hand, in the IRDL method, you use the insulating materials to cover the top metal and form VIA to open the pads. Then, you use aluminum to form lines, which is different from PKG RDL. Afterward, you apply insulating materials on top.

IRDL has the same purpose to relocate pads as PKG RDL. However, IRDL holds three major strengths courtesy of the RDL as the process progresses inside the FAB:

• Firstly, net die improves since circuits can be located under the pads.
• Secondly, the use of aluminum instead of gold lowers the cost of the entire process by up to 30%.
• Lastly, a chip’s performance is enhanced since circuit designer can utilize RDL for strengthening power mesh².

Figure 3. Comparing PKG RDL with IRDL

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Smaller chips better net die with circuits placed under the pad

When using the existing PKG RDL structure, numerous issues relating to the pad would often occur during probing and bonding, as the metal on top was too thin – under 1um level.
With the IRDL structure, it allows the thickness of the top metal almost 10um level enough to endure the stress generated during the probing and bonding, which allows placing the circuit under the pad. As a result, it can improve net die by reducing the chip’s size.

Reinforce PDN with IRDL

A reinforced power mesh using IRDL leads to power distribution network (PDN) enhancement, resulting in a much-improved chip performance. Without IRDL, PDN reinforcement can only be done with the chip’s existing metal wiring, causing PDN deterioration in far area from the pad. Reinforcement was therefore very limited with this method. On the other hand, when using IRDL, the freedom of reinforcement was greatly increased as it delivers a lower resistance value due to the nature of the RDL layer. Therefore, the performance of a chip can be improved by using IRDL.

IRDL: A Precursor for future devices

IRDL technology achieved a low-cost process with accomplishment on its main purpose of relocating IO pads to a position where PKG requires, without compromising an existing chip’s architecture. It has already made big contributions to SK hynix’s leading technologies in the mobile market, by decreasing the thickness of finished products. It allows the company to match the future direction of mobile devices – thinner products. Securing this element technology is crucial for the industry as a whole, as it advances net die by reducing its size and strengthens the performance.

¹MCP: Multi Chip Package, a technology that stacks more than two semiconductor chips into a single package to increase capacity and performance while reducing its mounting space – used predominantly for slim portable devices such as smartphones and tablet PCs. Thinner chips can be made during MCP using IRDL technology.
²Power mesh: A network that consists of power lines on multiple metal layers.

The post Inline Re-distribution Layer Tech Ignites a Chip Revolution first appeared on SK hynix Newsroom.