DRAMs fall under the larger category of Random Access Memories, or RAMs, which process data access randomly. Out of this group, the structure of DRAM is the simplest, allowing for high capacity, rapid read and write speed, and cost competitiveness. It is for these reasons that DRAMs are so popular in today’s market. However, a DRAM’s simple structure also means that data is stored within a capacitor, where data slowly exhausts over time. To manage this volatility, DRAMs require periodic data charging called ‘refresh.’

In general, DRAMs are classified into several fields, each evolving into their own optimized forms. This article will explore the growing fields of computing, mobile and graphic application memories.

Computing Memory

Computing memories used in PCs and servers are evolving high performance and high capacity data processing. Initially, Single Data Rate (SDR) DRAMs were used to send or receive just one data during one period of CPU system clock. As the CPU’s processing speed increased however, DRAM required faster processing speeds as well as higher memory bandwidth to keep up. Since then, the industry has advanced to Double Data Rate (DDR) DRAMs, which can process the data twice as fast – two times per one period . Over the years, the industry has iterated newer, faster products like DDR2, DDR3, DDR4, and DDR5, which have continued to accelerate clock speed.

In order to accommodate higher-capacity memory for servers, many are now using a Dual In-line Memory Module (DIMM) where multiple DRAM chips are mounted on a circuit board. Due to international standards and a long-established system configuration, DIMM has seen limited changes in form factors and power requirements over recent years.

Table 1. Specifications of Computing Memory

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Figure 1. DDR5 Module by SK hynix

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Mobile Memory

The explosive growth of mobile markets such as mobile phones and tablets has contributed to the development of the mobile application memory field. In mobile devices, battery power is essential. That’s why the industry developed Low Power Double Data Rate (LPDDR) DRAMs, low-power memory products that minimize battery consumption by reducing the leakage current in standby mode. Just like DDRs, LPDDRs have seen many iterations over the years. The LPDDR DRAM has evolved into LPDDR2, LPDDR3, LPDDR4, and LPDDR5 DRAMS, with each generation’s clock speed doubled and power efficiency improved, which is represented by power consumption over bandwidth.

Table 2. Specifications of Mobile Memory

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Figure 2. LPDDR4(X) by SK hynix

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Graphic Memory

Graphics Processing Unit (GPU) is specialized in parallel data processing. One memory chip is allocated to each GPU core, creating a channel which allows parallel processing. So in a multi-core structure, the bandwidth of each memory chip dictates system performance. The higher the bandwidth, the better the performance. To manage this, Graphics Double Data Rate (GDDR) memories, optimized for parallel operation applications, have been developed. Over the years, as demand for better bandwidth increased,they have evolved into GDDR2, GDDR3, GDDR4, GDDR5, and GDDR6.

Table 3. Specifications of Graphic Memory

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Figure 3. GDDR6 by SK hynix

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Memory Hierarchy

As seen in all of these series – from DDR to LPDDR and GDDR – DRAMs have been diversified greatly over time. Recently however, this evolution has slowed, with the improvement of performance and capacity becoming an increasingly difficult task.

To overcome this, the development of DRAMs is forging a new path through diversification of memory hierarchy. This “revolutionary path” has two directions: High Bandwidth Memory and High Capacity Memory.

Figure 4. Revolutionary Path and Evolutionary Path

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Figure 5. Memories for the Revolutionary Path

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※ Reference. Revolutionary Path and Evolutionary Path (Source: Presentation material “Technology Scaling Challenges and Opportunities of Memory Devices” by CEO Seok-hee Lee, at IEDM)

To deal with the demand for a larger bandwidth, High Bandwidth Memory (HBM) delivers a new tier between the last level cache of CPU and DRAM . Based on Through Silicon Via (TSV) technology, HBM has been developed to establish next-generation. HBM is mainly used in graphics, network, and HPC (high performance computing).

While it has advantages in high bandwidth and applicability compared to GDDR, it has some disadvantages in price, capacity, and application difficulty as well. That’s why many graphic card manufacturers are selectively adopting GDDR and HBM according to the application fields. Given the role of GPUs in the deep neural network field for artificial intelligence (AI) and machine learning (ML), GDDR and HBM are also expanding their application range into these areas.

Table 4. Specifications of High Bandwidth Memory

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Figure 6. HBM2E by SK hynix

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Meanwhile, a High Capacity Memory (HCM) delivers a new tier between DRAM and NAND Flash. As regard for the High Capacity Memory, there are two commercially developed solutions. One is a managed DRAM solution, which combines DRAM and a memory controller that improves internal timing for the expansion of capacity. The other one is equipped with a storage class memory such as Phase Change Memory (PCM), which has advantages in density compared to DRAM. High Capacity Memory is provided to customers in the form of a solution combined with a controller to ensure reliability, availability, and serviceability (RAS).

In the system industry, there have been various movements to utilize HCM. In particular,Compute Express Link (CXL), open interconnect consortium created primarily by Intel in 2019 has been driving discussions for actual adoption of HCMs in major data centers, servers, and SoC providers.

Along with HBM and HCM, the need for memories in autonomous vehicles and AI/ML application will likely increase as well. This change may be an opportunity for memory manufacturers to expand the market. At the same time, however, the pressure to develop products and the demand in new technologies increase simultaneously in order to correspond to the diversifying market.

Future Memory

SK hynix is focusing on developing advanced technologies to cope with memory technology changes. Also, the company is working with leading ICT (Information & Communication Technology) companies to make our lives more convenient. This work will act as a catalyst for the development of cutting-edge technologies that contribute to the progress of mankind.

The post Diversification of DRAM Application and Memory Hierarchy first appeared on SK hynix Newsroom.

The demand for mobile memory is steadily enhancing along with the consistent growth of mobile and wearable devices. When it comes to mobile devices, portability is pretty much everything which is why low-power and ultra-thin PKG technology has established itself as an essential element for the semiconductor industry.

Inline Re-distribution Layer (IRDL) technology is an advanced FAB technology that forms wiring by using an extra metal layer with an insulation layer and aluminum, enabling IO pads to relocate freely to the PKG wire bonding position where necessary. This technology allows you to make chip-to-chip bonding thinner and simpler. Additionally, IRDL, one of RDL technologies, was named so as the entire process takes place inside a FAB, unlike PKG RDL.
The figures below show the two MCP¹ methods for chips. “Vertical-Stack MCP” (left) is the existing technique where upper chips stack vertically on the lower chips’ bonding pad. “Shift-Stack MCP using RDL,” (right) on the other hand uses a shift-stacked method by avoiding the bonding pad. This way, wire interference and short from wire to chip that could occur within the vertical-stack MCP can be prevented. The gap between the upper chip and the lower chip reduces when this new method is applied, making it significantly easier to meet the proper thickness that the customers require.

Figure 1. Vertical-Stack MCP vs Shift-Stack MCP

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Figure 2. Cross-Sectional View of Figure 1

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Comparing existing PKG RDL and IRDL processes

The major difference between PKG RDL and IRDL lies within the structure formation method, so let’s learn more about the benefits of IRDL.

PKG RDL’s structure formation method is largely divided into two processes: FAB-in and FAB-out. The FAB-in process involves covering a top metal by an insulating material with only pads open. Then, in the FAB-out process, you apply the 1st dielectric layer to separate the RDL line from the insulating materials on top of the wafer, and form lines using gold. After that, a 2nd dielectric layer is applied to cover the top of the line.

On the other hand, in the IRDL method, you use the insulating materials to cover the top metal and form VIA to open the pads. Then, you use aluminum to form lines, which is different from PKG RDL. Afterward, you apply insulating materials on top.

IRDL has the same purpose to relocate pads as PKG RDL. However, IRDL holds three major strengths courtesy of the RDL as the process progresses inside the FAB:

• Firstly, net die improves since circuits can be located under the pads.
• Secondly, the use of aluminum instead of gold lowers the cost of the entire process by up to 30%.
• Lastly, a chip’s performance is enhanced since circuit designer can utilize RDL for strengthening power mesh².

Figure 3. Comparing PKG RDL with IRDL

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Smaller chips better net die with circuits placed under the pad

When using the existing PKG RDL structure, numerous issues relating to the pad would often occur during probing and bonding, as the metal on top was too thin – under 1um level.
With the IRDL structure, it allows the thickness of the top metal almost 10um level enough to endure the stress generated during the probing and bonding, which allows placing the circuit under the pad. As a result, it can improve net die by reducing the chip’s size.

Reinforce PDN with IRDL

A reinforced power mesh using IRDL leads to power distribution network (PDN) enhancement, resulting in a much-improved chip performance. Without IRDL, PDN reinforcement can only be done with the chip’s existing metal wiring, causing PDN deterioration in far area from the pad. Reinforcement was therefore very limited with this method. On the other hand, when using IRDL, the freedom of reinforcement was greatly increased as it delivers a lower resistance value due to the nature of the RDL layer. Therefore, the performance of a chip can be improved by using IRDL.

IRDL: A Precursor for future devices

IRDL technology achieved a low-cost process with accomplishment on its main purpose of relocating IO pads to a position where PKG requires, without compromising an existing chip’s architecture. It has already made big contributions to SK hynix’s leading technologies in the mobile market, by decreasing the thickness of finished products. It allows the company to match the future direction of mobile devices – thinner products. Securing this element technology is crucial for the industry as a whole, as it advances net die by reducing its size and strengthens the performance.

¹MCP: Multi Chip Package, a technology that stacks more than two semiconductor chips into a single package to increase capacity and performance while reducing its mounting space – used predominantly for slim portable devices such as smartphones and tablet PCs. Thinner chips can be made during MCP using IRDL technology.
²Power mesh: A network that consists of power lines on multiple metal layers.

The post Inline Re-distribution Layer Tech Ignites a Chip Revolution first appeared on SK hynix Newsroom.