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21st-century auto technology is undergoing a massive digital transformation that has been labelled the CASE revolution due to cars becoming more Connected, Autonomous, Shared, and Electric. Vehicles now come with complex and efficient interconnectivity as well as integrated systems, such as infotainment, long-life batteries, and ultra-fast 5G networks. By leveraging a myriad of leading-edge technologies, car manufacturers are pushing the boundaries of mobility with never-before-seen functionality.

Vehicle automation in particular has been a focal point for automakers with self-driving cars now capable of performing most driving tasks, providing drivers with unprecedented convenience. Level 3 automated vehicles that can steer, accelerate, and brake on their own under certain conditions are presently being rolled out. This is a significant leap beyond levels 1 and 2 vehicles which offer driver assistance and Advanced Driver-Assistance Systems (ADAS) but still require steering and constant monitoring. Level 4 vehicles that can perform all driving tasks under certain conditions are currently in the developmental phase but are projected to find broader implementation by 2024 according to IDC.

Self-driving cars are fully loaded with electronic systems supporting an infrastructure, essentially making them mobile data centers that require an immense amount of computing power. The challenge automakers now face is creating data-storage subsystems that can handle advanced applications and meet automotive constraints. Semiconductors that have long powered the smartphone industry are currently being adapted into auto-grade memory and integrated into autonomous vehicles. With their increasing storage capacity and speeds, these tiny but powerful chips are now crucial for self-driving vehicles, creating a massive demand for NAND and DRAM in the global automotive market.

What makes self-driving possible?

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Self-driving cars use sensors such as LiDAR, RADAR, Ultrasonic, and high-resolution video cameras to detect objects and signs, including vehicles, traffic lights, lane markings, pedestrians, and road edges, thereby creating a map of its environment. Vehicle-to-everything (V2X) technology enables the vehicle to communicate with everything nearby, including other vehicles, infrastructure, networks and pedestrians to further help construct this virtual map. Artificial Intelligence (AI) in the form of electronic control units (ECUs) then process and interpret all the sensory input and data before sending instructions to actuators that steer, brake, and accelerate as required. Sensors, V2X and AI technology all interact seamlessly together making self-driving vehicles a reality.

DRAM and NAND leading the smart car revolution

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The advanced technology embedded in self-driving cars require enhanced memory solutions due to the mission-critical nature of the applications and the immense amount of required storage. As people’s lives are on the line, there is no margin for error. This means auto-grade memory must be more reliable, faster, and robust than memory used in smartphones or laptops. Additionally, with self-driving cars projected to consume 5-20 TB per day per car, memory capacity must be increased to meet automotive needs.

To meet automotive-grade memory requirements LPDDR5 originally designed for mobile is being enhanced for self-driving vehicles, due to its many advantages including high density, performance, and endurance. LPDDR5 is being adapted for much larger dashboard displays to manage increasingly sophisticated navigational images and the control area of cockpit units. The digital cluster, front and rear sensors, and driver-monitoring system utilizing in-cabin cameras also require auto-grade LPDDR5.

High-capacity NAND flash memory, another key smartphone component, is playing an integral role in automotive applications and systems owing to its robust structure and multi-terabyte storage capabilities. Auto-grade NAND enables data capture and permanent storage of accidents in real-time as well as self-driving functions such as vehicle proximity alert, auto-headlights, speed regulation, emergency braking, lane integrity, and blind spot monitoring.

Meeting smart car industry standards

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According to the U.S. National Highway Traffic Safety Administration (NHTSA), of all serious motor vehicles crashes, 94% were due to human error. Self-driving vehicles not only offer more convenience but the ability to reduce crashes, prevent injuries and save lives. To ensure driver safety, automotive-grade memory must meet stringent quality standards that ensure memory chips are error free and can be relied upon even in extreme temperatures and dynamic conditions.

A key standard established by the Automotive Electronics Council (AEC) is AEC-Q100, a failure mechanism based stressed test qualification that guarantees a certain level of reliability and longevity for integrated circuits (IC). Stress testing of memory components concerns not only in-vehicle usage but the design and manufacturing process to ensure the highest quality product. To meet AEC-Q100 requirements, chip integrity is measured through a battery of stress tests involving temperature, vibration, and conditions such as dust and condensation. Only after passing all tests is a component certified auto-grade.

SK hynix has dedicated itself to achieving AEC-Q100 qualification by building up its process from the R&D stage to manufacturing using automotive industry standards. One such standard is IATF-16949, the Quality Management Systems standard for the automotive industry, which emphasizes defect prevention and reduction of variation and waste. Another industry standard SK hynix follows is ISO-26262, a mandate to develop a functional safety process to reduce the possibility of electrical malfunction. Additionally, Automotive Software Performance Improvement and Capability Determination (ASPICE) is an established framework used by SK hynix for measuring process quality.

Keeping pace with automotive memory needs

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With the advancement of self-driving cars, data storage has become a critical component of automotive design. This has placed a precedence on high data retention, speed and continual data integrity for the systems that make autonomous cars possible. As a developer of advanced, high-quality memory products, SK hynix stands at the forefront of this movement and is enhancing DRAM and NAND for the automotive market. In doing so SK hynix has positioned itself as a leader in the new e-mobility era and is committed to the ultimate goal of delivering safety and convenience to all drivers.

The post Let’s Hit the Road: Automated Vehicles are Pulling into the Fast Lane first appeared on SK hynix Newsroom.

It is the reason that our company carries an incredible influence in the memory market, and continues to push the envelope year over year, often topping our past accomplishments. This past December, we decided to raise the bar again with the completion of developing the industry’s most multilayered 176-layer 512 Gigabit (Gb) Triple-Level Cell (TLC) 4D NAND flash.

Our engineers, developers, researchers and strategists continue changing the game, and it is why we have a proven track record of bringing exceptional, high-performance, reliable products to market. In this article, we let you hear from our talented team first-hand about what it is like to raise the bar once again.

Meet the Experts

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Doogon Kim
Project Leader (PL), NAND Development, Design

What was your role in the development of the 176-Layer NAND Flash?

• “I am in charge of designing 176-Layer 4D 512Gb TLC Core/Analog, securing the world’s No. 1 Net Die, timing performance and power competitiveness. I introduced a 2-division cell array selection technology in order to overcome the deterioration of Program/Read performance due to the increase of Core Loading coming from the technology development in 4D NAND Flash.”

What improvements have been made in the 176-Layer 4D NAND Flash compared to previous products?

• “It significantly contributed to the cost competitiveness by improving ‘Bit Growth’ compared to the previous products, and it enhances the performance by 15% in Program/Read performance improvement solutions.”

How will the new 176-Layer 4D NAND Flash immediately benefit the industry?

• “I believe that 176-Layer NAND Flash products can activate more distribution of NAND Flash products in our everyday lives. It is the world’s best performance and cost competitiveness through improved bit growth.”

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Byeongchan Bang
Technical Leader (TL), NAND Development, PI (Process Integration)

What is the role of your work as a technical leader in the development of the 176-layer 4D NAND flash?

• “I work on the Gate-2 Module within the Progress Integration (PI). PI engineers of modules design, optimize, and improve the module unit process or the entire process to satisfy the specifications in terms of performance/reliability/quality in product development.”

What was the most difficult part when developing the technology? How did you overcome that?

• “When the height between cell layers is reduced, the basic characteristics of the cell deteriorate (increased resistance and interference between cells), which makes the process more difficult; However, the unit process problem is affected by the plug hold process, which divides the layers into very vulnerable ones and less vulnerable ones. Using the difference between layers, we overcame the problem by partially increasing the height between weaker cell layers only.
In other words, the height between cell layers was reduced overall, but we’ve increased the height between the cell layers that are vulnerable to performance and process problems.”

How do you expect the daily lives of those who use the 176-layer product to improve?

• “The 176-layer product is a high-capacity, high-performance (1.6 Gbps speed target) product. Those who use the 176-layer product will be able to use a larger capacity of the memory at a higher speed. Ultimately, in line with the recent 5G era, they will be able to experience faster data storage and transmission.”

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Wonyeol Choi
Project Leader (PL), NAND Development, PnR

How long have you worked at SK hynix and what is your role?

• “I have been with the company for 21 years, and my main role is to optimize the characteristics of NAND cells to improve the yield and achieve a certain level of performance. However, to play the role properly, collaboration with the related departments is very important. For this reason, I pay the most attention to playing the role of a channel to maximize the synergy of collaboration between devices/processes/designs/products.”

What effect do you think the 176-layer product will have when other NAND products are developed in the future?

• “The 176-layer product increased the degree of freedom in development by breaking the link as follows: Increasing the number of stacks, the method adopted by existing 3D products -> Increase in the number of available voltages + Increase in the number of groups by floor -> Increase in chip size -> Weakened product competitiveness.”

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Sanggil Lee
Technical Leader (TL), NAND Development, Process

What is your unique role on the team?

• “I am a photolithography engineer, and I implement fine patterns by making alignments between the lower layer and the current layer. My main task includes new device development setup and scheme development. The main things I manage include CD, overlay, and defect control.”

What was your priority when planning the 176-layer product?

• “In a situation where the number of NAND stacking layers was continuously increasing, I focused on implementing process management using the technology equivalent to or better than the existing company. Also, I focused on improving the process margin by developing materials and equipment (including measurement methods) to enable mass-production of the product. When developing 3D/4D NAND, I put importance on how to accurately correct the real cell between high layers in particular.”

Which customers will benefit most thanks to the 176-layer product?

• “The product will be used to benefit those in the high-capacity, high-efficiency SSD market.”

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Hyeyoung Lee
Technical Leader (TL), NAND Product Planning

How long have you been with the company, and what was your role in the development of the 176-Layer NAND Flash?

• “I have been working at SK hynix for 17 years since 2004. In this project, I selected the density of this product based on the review of the NAND Market and solution line-up. Afterwards, I reviewed NAND/Solution line-up in detail, discussed the spec target under discussion and consultation with the relevant departments.”

What was the most important part when planning the 176-Layer NAND Flash products?

• “A performance target setting according to cost reduction compared to existing technology and introduction of IO speed 1.6Gbps. Thanks to this, we expect improved performance of the solution’s sequential read and random read.”

How will 176-Layer 4D NAND Flash improve people’s everyday lives?

• “We expect to see the increase of the storage capacity in smartphones and laptops with the cost reduction at 176-level.”

Layer by layer

We will continue to lead the 4th industrial revolution with top-tier technology and overcoming obstacles brick-by-brick and layer-by-layer. SK hynix is the pioneer of 4D NAND, and we will continue to lead the NAND flash market with the industry’s highest productivity and technology.

Innovation is at the core of all our products – and at the core of our entire business philosophy. In the near future, we plan to consistently enhance our competitiveness in the industry by developing another advanced product based on 176-layer 4D NAND and raise the bar once more.

The post Why SK hynix continues to raise the bar first appeared on SK hynix Newsroom.

SK hynix Inc. (or ‘the Company,’ www.skhynix.com) announced the completion of developing the industry’s most multilayered 176-layer 512 Gigabit (Gb) Triple-Level Cell (TLC) 4D NAND flash. The Company provided the samples to controller companies last month to make a solution product.

SK hynix has been promoting 4D technology from the 96-layer NAND flash products that combine Charge Trap Flash (CTF) with high-integrated Peri. Under Cell (PUC) technology. The new 176-layer NAND flash is the third generation 4D product that secures the industry’s best number of chips per wafer. This allows the bit productivity to be improved by 35% compared to the previous generation with the differentiated cost competitiveness. The read speed of cell increased by 20% over the previous generation adopting 2-division cell array selection technology. The data transfer speed also has been improved by 33% to 1.6Gbps adopting speed-up technology without increasing the number of processes.

Starting with mobile solution products that have improved maximum read speed by 70% and maximum write speed by 35% in the middle of next year, SK hynix plans to release consumer and enterprise SSDs sequentially expanding its application market of the products.

As the number of layers increases in NAND flash, the cell current reduction, the channel hole twisting, and the cell distribution deterioration due to double stack misalignment occur. SK hynix overcame these challenges by adopting innovative technologies such as cell interlayer height reduction, layer variable timing control and ultra-precise alignment and developed the industry’s top tier 176-layer NAND flash.

The Company also plans to consistently enhance its competitiveness in the NAND flash business by developing 1 Terabit (Tb) products with doubled density based on 176-layer 4D NAND.

“NAND flash industries are striving to improve technologies for high integration and maximum productivity at the same time,” said Jung Dal Choi, Head of NAND Development at SK hynix. “SK hynix, as a pioneer of 4D NAND, will lead the NAND flash market with the industry’s highest productivity and technology.”

According to market intelligence provider Omdia, the NAND flash market is estimated to expand from 431.8 billion GB in 2020 to 1.366 trillion GB in 2024 with 33.4 percent Compound Annual Growth Rate (CAGR).

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Annotation

■ 4D NAND
SK hynix has named ‘4D NAND Flash’ to highlight the differentiation that achieves both performance and productivity at the same time by combining CTF cell structure and PUC technology from 96-layer NAND Flash in 2018.

■ Charge Trap Flash (CTF)
Unlike floating gate, which stores electric charges in conductors, CTF stores electric charges in insulators, which eliminates interference between cells, improving read and write performance while reducing cell area per unit compared to floating gate technology. Most 3D NAND companies are adopting CTF.

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■ Peri. Under Cell (PUC)
A technology that maximizes production efficiency by placing peripheral circuits under the cell array.

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■ 2-division cell array selection technology

The word line applies a voltage to the cell in the NAND flash circuit. The more the number of layers, the thinner the word line is to lower the cell’s height, and the greater the resistance applied to the word line will affect the speed. By dividing the cell connected to the word line into half compared to the existing one, the resistance can be lowered, which shortens the time of applying voltage and improves the read speed.

■ Cell interlayer height reduction technology

As the number of layers increases, it becomes difficult to drill holes for cell formation. This leads to increased resistance and reduced current, making it difficult to secure performance and reliability. For this, it is necessary to lower the cell interlayer height as much as possible, but this can increase interference between cells and defect rate. The cell interlayer height reduction technology not only dramatically lowered cell interlayer height of 176-layers but also secured competitive performance/reliability with related processes and design technologies.

■ Layer variable timing control technology

Increasing the number of layers and lowering the layer height often leads to channel hole twisting and cell scattering deterioration, which degrades the performance and reliability of each layer. This technology adjusts the amount and time of voltage applied according to the characteristics of each layers to maintain uniform cell characteristics and improve performance and reliability.

■ Ultra-precise alignment technology

Industries are utilizing a double-stack process that drills holes twice because it is impossible to drill holes for cell formation at once as the number of layers increases. Minimizing double-stack misalignment is the core of the double-stack technology. If the stacks are not aligned correctly, it will result in poor flow of current between stacks and occurrence of deterioration, reducing yield rate, performance and reliability. SK hynix applied double-stack technology since its 72-layer product in 2017, to this 176-layer product and advanced a technology that automatically corrects the location and size of holes in real time based on its know-how.

About SK hynix Inc.

SK hynix Inc., headquartered in Korea, is the world’s top tier semiconductor supplier offering Dynamic Random Access Memory chips (“DRAM”), flash memory chips (“NAND flash”) and CMOS Image Sensors (“CIS”) for a wide range of distinguished customers globally. The Company’s shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxemburg Stock Exchange. Further information about SK hynix is available at www.skhynix.com, news.skhynix.com.

Media Contact

SK hynix Inc.
Global Public Relations

Technical Leader
Sejin Julia Yoo
E-Mail: global_newsroom@skhynix.com

Technical Leader
Jaehwan Kevin Kim
E-Mail: global_newsroom@skhynix.com

Technical Leader
Eun Suk Yixi Lee
E-Mail: global_newsroom@skhynix.com

The post SK hynix Unveils the Industry’s Most Multilayered 176-Layer 4D NAND Flash first appeared on SK hynix Newsroom.