In this EE Times article, Ki-ill Moon, the head of PKG Technology Development at SK hynix, covers the evolution of packaging technology and highlights some of the company’s recent efforts and accomplishments in helping to advance the field.

As the speed, density, and functions of a semiconductor product vary depending on how the interconnection is made, interconnection methods during the packaging process are constantly changing and developing as mentioned by Moon in his previous article.

More specifically, the following four types of interconnection techniques have gradually developed over time to eventually provide more efficient and high-quality packaging techniques: wire bonding, flip chip bonding, through-silicon via¹ (TSV) bonding, and hybrid bonding with chiplets.

¹Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

With traditional wire bonding technology advancing all the way to the more recent hybrid bonding with chiplets, unprecedented achievements have been made through improvements in the package’s cost-effectiveness, operating speed, flexibility of chip design, thermal dissipation, and size reduction.

Following such developments, SK hynix developed the world’s first-ever 12-layer HBM3 in April 2023. Furthermore, the company plans to use the most high-powered packaging solution to develop hybrid bonding so it can be applied to its future HBM products such as the 16-layer HBM.

To find out more about the technologies that will help SK hynix elevate its packaging technologies and platform solutions to unprecedented levels, read the full EE Times article here: The Role of Interconnection in the Evolution of Advanced Packaging Technology

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Packaging technology has four main functions. It protects the semiconductor chip from external shock or damage, provides external power and wiring to the chip, and properly distributes heat generated by the chip to ensure stable operation. Additionally, packaging technology acts as a bridge by connecting the gaps existing between semiconductor devices and systems.

Over the past two decades, packaging technology has evolved significantly. These developments include stacking multiple chips onto one package and including chip bumps for interconnection that shortened the signal path to achieve faster operating speeds. Most recently, packaging technology can be considered a system solution by itself as it’s capable of connecting various types of chips into one package and many parts into one module when incorporating a system.

In this EE Times article by Ki-ill Moon, head of Package Technology Development at SK hynix, the author details how SK hynix’s packaging technologies such as Chip-on-Chip (CoC) and Mass Reflow Molded Underfill (MR-MUF) produced vast improvements in speed, cost, and quality.

Today, SK hynix is leading the packaging revolution as it has been mass-producing advanced packaging products based on HBM3 and focusing on investing in production lines and securing resources for the development of future packaging technologies such as heterogenous integration and Fan-out RDL.

As SK hynix always strives to maintain its leadership position in today’s semiconductor memory industry, the company will continue to make innovative efforts to advance its packaging technologies and become a total “solution provider.”

Learn more about the evolution of packaging technology by reading the EE Times article: The Value of Semiconductor Packaging Technology in the Era of Heterogeneous Integration

The post The Value of Semiconductor Packaging Technology in the Era of Heterogeneous Integration first appeared on SK hynix Newsroom.

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It’s very challenging to further miniaturize components that are already only a few nanometers wide.

The history of electronics is a study in the progression and evolution of miniaturization, as electrical systems matured and migrated to become what we now consider electronics. The reason older tech is huge is that it was full of individual components that were literally wired together. All of the electronics processes that we do today, with digitally driven solid-state devices, had to be done in a brute-force analog manner.

In the case of the transistors that make up our modern microcontrollers and processors, the antique analog versions were called vacuum tubes [1], variations on light bulb technology originally discovered in 1880 by Thomas Edison. Exited metal plates between filament grids in the vacuum-sealed glass bulbs regulated the passage of current but were very power inefficient (because they were modified light bulbs) and very fragile (also because they were modified light bulbs).

Figure 1. Circuit diagram of the Edison discovery.

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These issues of power and size in electronics were such a fundamental aspect of early electronics that it shaped both popular and professional history. The first computers and their rows upon rows of vacuum-tube-filled racks engulfed a large room and gave off so much heat that the first computer bug reported was an actual insect attracted to the tubes [2]. Even in science fiction, an art designed to inspire futuristic thought, most authors predicted powerful computers—none predicted small pocket-sized smart devices.

Kilby, Noyce, and the Birth of the Chip

The discovery of the semiconductor and the creation of solid-state transistors in the 1960’s began the evolutionary process in electronics [3], laying the foundation for the world we have today. Instead of using a brute-force approach of wires and grids in a vacuum tube, a semiconductor device works by controlling the passage of electrons through a solid monocrystalline piece of semiconducting material. (There is an entirely different revolution going on in semiconductor materials, which we’ll touch on later.)

These semiconductor devices, even in their first iterations, were significantly smaller, lighter, better performing, cooler operating, and much more efficient than their glass-based forefathers. The breakthrough in semiconductors enabled the creation of the integrated circuit (IC), although there were several important technology hurdles that had to be overcome. These included the actual forming of devices in the crystal, the need to electrically isolate components, and the creation of electrical connections within the IC.

The birth of the IC is a story in parallel development. Jack Kilby, a radio engineer and World War II veteran, made the first hybrid IC in May 1958 from germanium [4], followed closely in January of 1959 by Robert Noyce, who unveiled his design of a planar integrated circuit [5]. Since then, semiconductor devices have been continuously miniaturizing.

Later on, in the early 70’s, IC feature device size (the space between the components and connection vias) decreased to 10 μm, and the number of the MOSFETs in a chip exceeded 1,000 [6]. In modern days, chips have gone down to 7nm spacing, with 5nm planned, and work underway for 2nm and less.

I/O, Logic, and Power

There are many aspects that need to be addressed when making electronics smaller in general, including the integration and management of the data input/output (I/O), the logic IC itself, and the power needed to drive it all. The demands of each create a juggling act the electronic designer must perform when creating products.

At the circuit-board level, miniaturization involves high levels of component integration. For example, a product could require an inertial sensor, a compass, temperature and presence sensors, as well as those for images and light. An integrated sensor module groups sensors based on related technologies into a single package, saving significant space.

Meanwhile, package-level miniaturization forces include the shrinking of power electronics due to the advent of new wide-bandgap semiconductors. These new materials, Gallium Nitride (GaN) and Silicon Carbide (SIC) are enabling a 60%+ reduction in the size of power supplies while also increasing performance by up to 300% [7]. They are enabling significant reduction in products simply by making the power electronics smaller.

We must consider the circuit-level miniaturization process as well, which relies on simplifying and/or optimizing the system. This approach leverages advances in device integration and the new power electronics, which enable advanced circuits with smaller passive devices and significantly smaller footprints. It can be leveraged with next-generation user interfaces that eliminate the need for a keypad or other space-hungry input method.

When it comes to logic devices, all issues at the macro-level must also be addressed at the chip level. How many devices can be integrated on a chip? How closely can the components of a chip be put together before they start interfering with one another? How do you get power in the right amount (current) and level (voltage) to the parts of the chip that need it?

Shrinking the Chip

There are several limiting factors when it comes to miniaturization. The first limit is defined by basic physics, in this case the distance of atoms in the material. It’s literally impossible to make the device structures less than the atomic distance, which does define a true lower limit to nano-electronics. This lower limit isn’t the real final barrier to miniaturization, however, as there is a fundamental limit defined by the distance the electrons can tunnel in the material.

The smaller chips get, the harder it is to control aspects like the leakage current between the source and drain of the transistors involved. This is regarded as one of the main limits to miniaturization, because it’s impossible to suppress the diffusion of electrons from the source to the channel at normal temperatures.

Still, the industry will continue to shrink electronic devices of all types because they are critical to so many aspects of our future smart Cloud-enabled Internet of Things (IoT)-oriented society. Both at the macro-level and the micro-level, expect to see higher levels of component integration, both planar and 3D, as well as further advances in materials for both the chips and their interconnects.

In the sense of vertical integration, SK hynix’s 176-layer 512 Gigabit (Gb) Triple-Level Cell (TLC) 4D NAND flash is a good example of the current state of the art [8]. The third generation 4D product that allows the bit productivity to be improved by 35% and the read speed increased by 20% over legacy devices. The data transfer speed also has been improved by 33% to 1.6Gbps without increasing the number of processes.

Figure 2. SK hynix’s 176-layer 512 Gb TLC 4D NAND Flash

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In regard to material advancements, just as piezoelectric semiconductors like Gallium Nitride have revolutionized the power electronics industry, they offer the promise to do the same for logic chips. One of the major benefits of a piezoelectric semiconductor is its ability to switch at extremely high speeds. Currently advanced GaN power devices can switch up to 40 MHz [9], and if these materials can be adapted to logic circuits, could enable a jump of several orders of magnitude in processor performance at the same feature size.

Another area of approach to miniaturize chips is to improve the way we flash the mask pattern onto the wafer itself. The more we can improve pattern resolution, the closer we can get to the theoretical limits in smaller sizes. The latest lithography methods [10] use short wavelengths in the blue or ultraviolet range.

Figure 3. A diagram of EUV equipment

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For instance, in the semiconductor memory industry SK hynix recently announced the mass production of its cutting-edge 1anm 8Gb LPDDR4 DRAM by using EUV equipment [11]. As one of the first to successfully implement the technology in mass production, several other major manufacturers are expected to follow in SK hynix’s footsteps as confidence grows in the application of EUV.

Figure 4. SK hynix’s 1anm 8Gb LPDDR4 DRAM Using EUV Equipment

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Integration is key

Another aspect of design where the micro mimics the macro is in the integration of functionality. Just as a product can be made smaller by integrating various devices on the circuit board, the circuit itself can be made smaller by integrating function blocks into the chip.

By providing functions that used to require their own device, highly integrated chips enable a significant reduction in the board space used [12]. Where once even a “simple” smart product needed a microcontroller (MCU), a power management IC (PMIC), an RFIC, and a chip to control the user interface at the least, can now be served by a single-chip solution, requiring only a display, antenna, and a battery (packaging too) to create a basic product.

All of the developments in component integration, next-generation functionalities, and even packaging advances come together to create the micro-product revolution going on as you read this. Another often-overlooked aspect in the effort to shrink a product involves flexible electronics. Making flat, flexible, and efficient electronics opens the door to countless smart products that were impractical due to size or form-factor issues.

The ability to bend, fold, roll, and even stretch will enable electronics to not only expand more deeply into market sectors like medical and sports wearables, advanced portable and small robotics applications, and the Internet of Things, it will also enable those products to be rolled up and/or folded and easily stored between uses. Optimizing a product design by highly integrating its functionality at the chip, board, and product level pays major dividends.

Bulky keyboards and large screens will eventually cease to be a size issue when flexible electronics and non-contact means of data entry are further commercialized. Reducing the impact of the user interface on product design cannot be underestimated, as every external opening is removed not only reduces the form factor demands, but also increases water resistance and product durability. Optimizing a product design by highly integrating its functionality at both the chip and board level pays dividends at each.

Looking Forward

The advanced electronics and the semiconductors behind them are the sophisticated result of decades of research and development, both in functionality and scaling. The demand for smaller and smaller technology will never diminish, as the new functionalities delivered today create new expectations for tomorrow. The semiconductor industry must continue in its efforts to innovate and keep shrinking electronic components to keep pace with the demands of society in the areas of technological advancement, in even the tiniest of ways.

[Reference]

[1] ScienCentral. (n.d.). The Vacuum Tube. ScienCentral and The American Institute of Physics, 1999. https://www.pbs.org/transistor/science/events/vacuumt.html
[2] National Geographic Society. (2014, July 18). World’s First Computer Bug. https://www.nationalgeographic.org/thisday/sep9/worlds-first-computer-bug/
[3] The semiconductor revolution. (n.d.). Encyclopedia Britannica. https://www.britannica.com/technology/electronics/The-semiconductor-revolution
[4] Kilby, J. (n.d.). Jack Kilby Biography. NobelPrize.Org. https://www.nobelprize.org/prizes/physics/2000/kilby/biographical/
[5] Lovos, M. (2018, June 7). Robert N. Noyce Biography. IEEE Computer Society. https://www.computer.org/profiles/robert-noyce
[6] The Electrochemical Society. (2021, April 13). Impact of Micro-/Nano-Electronics, Miniaturization Limit, and Technology Development for the Next 10 Years and after. Newswise. https://www.newswise.com/articles/impact-of-micro-nano-electronics-miniaturization-limit-and-technology-development-for-the-next-10-years-and-after
[7] Navitas. (2021, August 27). SHARGE Upgrade 100W Fast Charging: 60% Smaller than Legacy Silicon. https://navitassemi.com/navitas-and-sharge-upgrade-100w-fast-charging-60-smaller-than-legacy-silicon/
[8] SK hynix Unveils the Industry’s Most Multilayered 176-Layer 4D NAND Flash. (2020, December 24). SK Hynix Newsroom. https://news.skhynix.com/sk-hynix-unveils-the-industrys-highest-layer-176-layer-4d-nand-flash/
[9] Jha, J., Ganguly, S., & Saha, D. (2021, May 12). GaN-based complementary inverter logic gate using InGaN/GaN superlattice capped enhancement-mode field-effect-transistors. IOP Science. https://www.scribbr.com/apa-citation-generator/new/webpage/
[10] Markoff, J. (2015, September 26). Smaller, Faster, Cheaper, Over: The Future of Computer Chips. The New York Times. https://www.nytimes.com/2015/09/27/technology/smaller-faster-cheaper-over-the-future-of-computer-chips.html
[11] SK hynix. (2021, July 12). SK hynix Starts Mass Production of 1anm DRAM Using EUV Equipment. SK Hynix Newsroom. https://news.skhynix.com/sk-hynix-starts-mass-production-of-1anm-dram-using-euv-equipment/
[12] A Trend Towards Miniaturized Electronics A Trend Towards Miniaturized Electronics. (2021, May 10). ROHM Semiconductor. https://www.rohm.com/blog/miniaturized-electronics

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1. Package Development Flow

Figure 1. Changes in the number of semiconductor packaging pins (or balls)
in contact with the system board

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To develop a new semiconductor package, the way of mounting the package on a system board and the external form of it must be changed. Then, the internal structure and material of the package must also be altered. When a package structure becomes complicated, the more the number of pins or balls in contact with the system board, the less the ball pitch – the distance between balls. The number of contact points between the package and the system board has rapidly approaching its limit and saturation point.

2. Package Structure

Figure 2. Internal and external structure of semiconductor package

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A semiconductor package’s structure consists of a semiconductor chip, a carrier (package PCB, lead frame, etc.) on which the chip is placed, and a molding compound which surrounds them.

In addition, the internal and external connection routes serve to connect signals from internal chips to the outside. Whether it be an internal or external connection, this connection was previously made with lines (wires or lead frames). Recently, however, points (bumpers or balls) are typically being used. Meanwhile, molding compounds play an important role in taking out the heat inside and protecting the chip from external damage.

3. Three Elements Determining Package Types: Internal Structure, External Structure and Mounting

Figure 3. Diagram of package internal connection type, external
connection type and mounting method

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Until the late 1980s, the mainstream package internal connection type was the wire bonding method, which connects the pad on the chip to the pad on the carrier with gold wires. However, as package sizes decreased, the volume occupied by the metal wires within the package increased with it. To solve this problem, instead of removing the metal wires, bumps were used to replace them for internal connections. Of course, that does not mean the wire bonding method became completely unavailable. When bumps are used, it requires the bump attaching process and epoxy under-fill methods instead of the die-attaching and wire bonding processes.

The external connection type has also shifted from the use of lead frames to balls. This is because lead frames have the same disadvantages as wires. While the “wire – lead frame – PCB through-hole mounting” was used before, now the method of “bump – ball grid array (BGA) – surface mounter technology” is the most commonly utilized.

4. Internal Package Type
4.1 Wireless Semiconductor, Flip Chip

Figure 4. Comparison of wire bonding type and flip chip type

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Semiconductor packages can be classified according to internal structure: wiring and flip chip. The wiring method connects the chip and the carrier through wire bonding, with a face up. On the other hand, the flip chip method involves very small diameter balls (a conductive metal called “bump”) being connected to the pad with a face down. In other words, with the flip chip method, the semiconductor chip is in contact with the board without the use of long wires. For this reason, it features a shorter signal travel distance and a more powerful adhesion strength. It is a groundbreaking method in that it addresses the various problems usually associated with wiring.

The greatest advantages of the flip chips are that they reduce the volume of the package and improve the power consumption and signal flow. Due to its shorter length, there are less effect of electrical resistance and noise from the surrounding area, making it faster. Also, what kind of metal a bump is important. Currently, solder or gold is typically used. Deciding what kind of epoxy material to fill the gap between bumps and carrier is another important matter. Besides, since it doesn’t use wires that occupy a large area, the size of the chip after molding can be reduced. This is why it is widely used in small electronic devices like mobile phones. That is, as the footprint area of the package on the system board is reduced, it is applied to high-density board technology. This means a major transformation in the packaging method, with the advent of miniaturized electronic devices such as smartphones.

4.2 TSV (Through Silicon Via), 3D Package Made by Draining Holes in Chips

Figure 5. 3D Package with Via Hole penetrating silicon chips

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We utilize a multi-layered packaging that stacks multiple semiconductor chips to increase the density of the chip package. Multi-chip packaging at the wafer level includes the wire bonding method and Through Silicon Via (TSV). In TSV, once chips are stacked, then you drain holes through them vertically to connect signal lines by using silicon through electrodes. Through this method, the speed of signals is faster and the density of the package can be higher. If the existing method of handling one single chip is regarded as 2D packaging, TSV can be considered 3D packaging. If multi-layered chips are connected with wires, a step-stack structure is formed, increasing the area by about two times. However, in TSV, a direct-stack structure is formed like an apartment building, requiring only around 1.2 times the chip area. TSV, which has excellent area efficiency, is now expanding its application to other fields.

5. External Package Type and Mounting Methods @Based on How the Package Connects to the Outside

Figure 6. Types of external package type and mounting methods

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5.1 External Package Type

Figure 7. IC Package Types

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There are numerous types of packaging chips. As a lead frame type, there is a dipping type suitable for PCB through-hole mounting, which has been developed in the order of SIP1, ZIP2, DIP3, and PGA4. However, since its ability to reduce the footprint area occupying the system board is limited, it is currently used only in some cases.

Meanwhile, among the lead frame types, small outline (SO) is one of surface mounter technologies where the lead is bent to increase the integration. It has been developed to SOIC and SOJ (J type) and is still used widely. In addition to this, a quad flat package (QFP) where the bent leads are applied on four edges is used in CPU chips. After that, the package changed dramatically from the lead frame type to the ball type, presenting a BGA. These days, the ball type is in the more mainstream system.

5.2 Mounting Methods

The package mounting methods are largely divided into surface mounter technology (SMT) and PCB through hole. As the name suggests, SMT fixes a chip to the system board surface via soldering. PCB through hole is a method of cutting a chip’s lead pins into a hole on the system board and then fixing it with soldering

In this method, however, the area occupied by holes on the system board was too large. For light, thin, short, and small packages, the mounting method has also been developed into a surface mounter technology without holes. Among the lead frame methods, SO type (SOIC and SOJ) and TSOP have been developed for surface mounting from the beginning. For the BGA type, it also applies the surface mounting method as well because the ball itself is for mounting on the system board.

Packages have been developing towards “light, thin, short and small packages”. To achieve this, the internal and external shape of the package and mounting methods are changing at the same time. In terms of power, speed, and environment, semiconductor package chips require a high level of performance. They are also transforming in terms of materials to satisfy this. The priority that packages change is usually structure, material, and function in order, but this doesn’t apply to all cases. Package types can be classified as follows: MCP (Multi Chip Package), SiP (System in Package), PoP (Package on Package), CSP (Chip Scale Package), and so on. On this wise, package types can be classified in various ways according to different perspectives. To avoid the confusion that can be caused by this, the structure of the packaged products has become the basis for classification in this chapter.

¹SIP (Single Inline Package): SIP is a package where the pins are arranged in a single row.
²ZIP (Zig-zag Inline Package): ZIP is a package where the pins are arranged in a zig-zag form.
³DIP (Dual Inline Package): DIP is a package where the pins are arranged in two rows.
⁴PGA (Pin Grid Array): PGA is a package with the square or rectangular shape, in which the pins are arranged in a regular array on the underside of the package.

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