Overview of Assembling Conventional Packages

Figure 1 shows the assembly process for plastic packages, which are a type of conventional package. Plastic packages are categorized into leadframe and substrate packages. The first half of the packaging process for these two packages is the same, but the second half differs in how the connection pins are applied.

▲ Figure 1. The steps of assembling leadframe and substrate packages (Source: Hanol Publishing)

Once the wafers are tested, they first go through backgrinding to become the desired thickness. Wafer sawing then follows so the wafers can be cut into chips. Afterwards, chips that are deemed to be of good quality are selected and attached to the leadframe or substrate through the die attach process. The chips are then electrically connected to the substrate through wire bonding before they are sealed with an epoxy molding compound (EMC) for protection. Both leadframe and substrate packages share these steps.

In the next stage, leadframe packages undergo several processes: trimming¹ that separates the leads, solder plating that applies solders to the ends of the leads, and, lastly, forming. The process of forming separates the packages into single units and bends the leads so they can be attached to the system board. As for substrate packages, they are molded before going through solder ball mounting where solder balls are attached to the substrate pads. This is followed by a process of cutting and forming individual packages called singulation. In the following section, the process of assembling conventional packages with an emphasis on the eight steps of producing substrate packages will be explained.

¹ Trimming: A process applied to leadframe packages that removes the dambar, which connects the space between the leads, using a cutting punch.

Step One: Backgrinding

The backgrinding process ensures a wafer is processed with the optimal thickness for its package’s characteristics. This includes processing the wafer’s back and mounting it to a ring frame, as shown in Figure 2.

▲ Figure 2. The four steps of the wafer backgrinding process (Source: Hanol Publishing)

Before grinding the backside of the wafer, a protective tape known as a backgrinding tape is laminated onto the wafer’s front. This is to prevent physical damage to the frontside where the circuit was formed. Next, grinding wheels are applied to the backside of the wafer to make it thinner. A rough grinding wheel is first used at high speed to remove most of the excess material before a fine grinding wheel grinds more delicately and accurately to reach the wafer’s target thickness. Afterwards, a fine pad is used for polishing to smooth the wafer’s surface. If the wafer’s surface is rough, cracks are more likely to occur when stress is applied during subsequent processes and result in the chip breaking. Therefore, it is crucial to reduce the chances of chip breakage by polishing that prevents the formation of cracks.

For packages consisting of a single chip, the wafer is generally grinded to a thickness of about 200 to 250 micrometers (μm). As for stacked packages, the chips—and essentially the wafers as well—need to be even thinner as multiple chips are stacked on the package. However, the residual stress from grinding the wafer’s backside causes shrinkage on the frontside and can potentially bend the wafer into the shape of a smile. Furthermore, the degree of bending becomes more severe as the wafer is thinned. To flatten out the wafer, mounting tape is first applied to the backside of the wafer and then it is attached to the ring frame. The backgrinding tape that was applied to protect the devices on the wafer’s front is then removed again, exposing the semiconductor devices to complete the backgrinding process.

Step Two: Wafer Sawing/Dicing

Wafer sawing is the process of cutting along the scribe lanes² of a wafer in order to break it into chips or dies. Also referred to as the dicing process, wafer sawing is a necessary procedure of the packaging process for chips or dies.

Figure 3 shows an example of a wafer being broken into chips through blade dicing, a method of wafer sawing that uses a wheel-shaped saw blade to cut and separate wafers. This saw blade with a wheel tip strengthened through diamond grit cuts along the wafer’s scribe lanes—the lattice-shaped lines of the wafer on the left of the figure. As the saw blade creates a working tolerance³ when it rotates, the scribe lane must be thicker than the wheel.

² Scribe lane: A space of sufficient width designated for cutting a chip or die from a wafer without affecting nearby devices while allowing for the distribution of the cut pieces.

³ Tolerance: The range of errors in space or values created from the difference of work capabilities.

▲ Figure 3. Sawing a wafer into chips through the blade dicing process (Source: Hanol Publishing)

One issue of blade dicing is that, as the blade physically contacts the wafers during the process, the wafers are more prone to breaking when they are requested to be made thinner. Laser dicing, another method of wafer sawing, resolves a lot of these issues as nothing physically contacts the wafer during the cutting process. Instead, a laser is shot from the back of the wafer during the dicing. Consequently, it is suitable for cutting thin wafers, while the chip remains robust due to the minimal damage to the wafer’s surface.

As wafers have become thinner, there have been proposals to use dicing before grinding (DBG) which reverses the sequence of processes to reduce chip damage during wafer cutting. While the conventional process involves thinning the wafer by backgrinding before it is cut, DBG is a different method that partially cuts the wafer before it goes through backgrinding and completely cuts it off through mounting tape expand⁴.

⁴ Mounting tape expand (MTE): Expansion of the mounting tape that is attached to the wafer after stealth dicing, a method of creating cracks in a wafer with a laser. Physical force is then applied to the relevant areas to break the wafer into chips.

Step Three: Die Attach

As shown in Figure 4, die attach is the process of picking up the chips that have gone through the wafer cutting process from the mounting tape and attaching them to a substrate or leadframe that has been coated with an adhesive.

▲ Figure 4. The die attach process (Source: Hanol Publishing)

During the wafer cutting process, the chip that has been cut should not fall off the mounting tape. However, in the attach process, the chip must be peeled off the mounting tape. As damage might be caused during the removal of the chip if the adhesion of the mounting tape is too strong, the adhesive should maintain a strong bond during wafer cutting and then weaken when it is exposed to ultraviolet light before the attach process. At this time, only chips that pass the wafer test are detached from the mounting tape.

While the removed chips must be reattached to the substrate with adhesive, there are differences depending on the type of adhesive used. If a liquid adhesive is used, it must be applied to the substrate in advance using a syringe-like dispenser or through stencil printing⁵. On the other hand, solid adhesives are usually in the form of a tape. Also known as die attach films (DAF) or wafer backside lamination (WBL) films, solid adhesives are especially preferred when chips need to be stacked. After backgrinding is complete, a DAF is attached between the mounting tape and the back of the wafer. When the wafer is cut, the DAF is cut along with it. As the DAF and the chip attached to its back will fall off, the DAF can be glued on top of the substrate or chip.

⁵ Stencil printing: A method of printing using a stencil mask to apply paste-type materials to devices such as substrates.

Step Four: Interconnection

Interconnection refers to the electrical connections between chips, chips and substrates, and other combinations within a package. The following section will introduce two interconnection methods: wire bonding and flip chip bonding.

▲ Figure 5. The seven steps of the wire bonding process (Source: Hanol Publishing)

Wire Bonding

Wire bonding uses heat, pressure, and vibration to electrically connect chips and substrates with metal wires. The wires are usually gold (Au) as they have good electrical conductivity and ductility. Wire bonding can be compared to sewing where the thread is the wire and the needle is the capillary⁶. The wire is rolled up onto a spool like a yarn and equipped to the machinery before it is pulled out and passed through the center of the capillary to form the tail at the end of the capillary. When the electronic flame-off (EFO)⁷ gives a strong electrical spark to the wire’s tail, that part melts and solidifies to form a free air ball (FAB) that is essentially caused by surface tension.

After the FAB is created, it is attached to the chip’s pad with force to form ball bonding. When the capillary is moved toward the substrate, the wire comes out like a thread to form a loop. Stitch bonding⁸ is formed by pressing the wire against the bond finger—the part of the substrate that will make the electrical connection. The wire is then pulled back even more to form a tail, and the connection between the chip and the substrate made with wiring becomes complete after the tail is cut. This procedure is repeated on the other chip pads and the substrate’s bond fingers during the wire bonding process.

⁶ Capillary: A tool used in wire bonding machines to connect chip electrodes and lead terminals with wires.

⁷ Electronic flame-off (EFO): A process which melts a wire tip by an electrical spark to form a FAB.

⁸ Stitch bonding: The bonding of wires to a pad during the semiconductor packaging process by pressing and attaching the wires.

Flip Chip Bonding and Underfill

Flip chip bonding creates a bump on top of the chip to make an electrical and mechanical connection with the substrate. Therefore, it has better electrical properties than wire bonding. There are two types of flip chip bonding: the mass reflow (MR) process and thermocompression. MR attaches the chip with the substrate by melting the junction’s solder at a high temperature. The thermocompression process, on the other hand, applies heat and pressure to the juncture to make the connection between the chip and substrate.

Since the stress caused by the difference in the coefficient of thermal expansion⁹ (CTE) between the chip and the substrate cannot be handled by the bump alone, an underfill process that fills the space between bumps with polymer is necessary to ensure solder joint reliability. There are two main underfill processes to fill up the space between bumps: post-filling, which fills the materials after flip chip bonding, and pre-applied underfill, which fills the materials before flip chip bonding. Additionally, post filling can be divided into capillary underfill (CUF) and molded underfill (MUF) depending on the underfill method. After flip chip bonding is applied, CUF fills in the gaps between bumps by using the capillary to inject underfill material into the side of the chip. As for MUF, it allows EMC to function as an underfill by using it to fill up the spaces between bumps.

⁹ Coefficient of thermal expansion (CTE): A material property that indicates the extent to which a material expands upon heating.

Step Five: Molding

Once the chip is wire bonded or flip chip bonded, it needs to be encapsulated to protect the structure from external impact. Such protection processes include molding, sealing, and welding, but only molding is used for plastic packages. The process of molding encloses EMC, which mixes thermosetting resin¹⁰ with several inorganic materials, around parts including chips and wires to protect them from physical and chemical external impacts and to create the desired package size or shape.

¹⁰ Thermosetting resin: A stable polymer material that undergoes a polymerization reaction when heated to harden and form a polymer compound. It is primarily used for EMC that protects the electronics and electrical properties of semiconductor circuits by preventing thermal and mechanical damage in addition to corrosion.

The molding process takes place in a mold. For transfer molding, a substrate with chips connected by wire bonding is placed on both molds while an EMC tablet is placed in the middle and heat and pressure is applied. This liquidizes the solid EMC to flow into both molds and fill up the space. Transfer molding faces challenges when the gap between the chip and the top of the package gets smaller as it becomes more difficult to be filled with a liquid such as EMC. Furthermore, when the substrate gets bigger, the mold has to increase in size accordingly and it therefore becomes harder for EMC to fill the space.

In recent years, the process of transfer molding reached its limits. As the number of chip stacks has increased while a package’s thickness has generally decreased, the gap between the chip and the top of the package has continued to shrink. The size of the substrate is also growing as more chips are being processed in large batches to lower manufacturing costs. For this reason, compression molding has emerged as the solution to filling the small gap. In compression molding, the mold is pre-filled with EMC powder. When heat and pressure are applied after the substrate is placed in the mold, the EMC powder filled in the mold liquidizes and is eventually molded. In this case, the EMC immediately becomes liquid and fills the space without flowing, so there is no problem filling the small gap between the chip and the top of the package.

Step Six: Marking

Marking is a process of engraving product information such as the semiconductor type or manufacturer, in addition to patterns, symbols, numbers, or letters requested by the customer, on the surface of semiconductor packages. This proves to be important when a semiconductor product fails to operate after it is packaged as the markings can assist in tracing the cause of the product’s failure. Markings can either be engraved by burning materials such as EMC with a laser or by embossing using ink.

For plastic packages, they need to be molded before the requested information is displayed on the surface. Since laser marking is simply the act of engraving, a black EMC is usually the preferred choice as it increases the legibility of the markings. This is because color cannot be applied to the engraved characters or symbols, so it is more visible to have engravings on a black background. The remaining two steps will cover the final stages of packaging substrate packages. This is where the difference lies between the processes of substrate and leadframe packages.

Step Seven: Solder Ball Mounting

Solder balls in a substrate package do not only serve as an electrical pathway between the package and external circuitry, but they also provide mechanical connections. Solder ball mounting is the process of attaching a solder ball to a substrate pad. In the first step of the process, flux¹¹ is applied to the pad and then the solder balls are placed on the pad. Then, the reflow process melts and attaches the solder balls before the flux is washed and removed. The role of the flux here is to remove impurities and oxides from the surface of the solder balls during the reflow process. This allows the solder balls to melt uniformly and provides a clean surface. When these melted solder balls flow into a stencil on the substrate, they fill each hole in the stencil. Then, the substrate and stencil are separated but the solder balls remain on top of the substrate due to the adhesion of the flux. As there will be flux that has already been applied to the pad, the solder balls will be temporarily adhesive and attach to the pad.

¹¹ Flux: A water-soluble and oil-soluble solvent that makes solder balls adhere well to the copper of the ball land.

▲ Figure 6. The temperature profile applied during the reflow process (Source: Hanol Publishing)

The solder balls attached to the substrate pad with flux melt through the reflow process. Figure 6 shows the temperature profile applied during this process. The flux is activated in the soak zone before the solder reaches its melting temperature, removing oxides and impurities from the surface of the solder balls. While the solder balls melt and attach to the pad when it is above the melting temperature, they do not flow off completely. Instead, they form a globular shape caused by surface tension in all areas except the parts where they adhere to the metal part of the pad. As the temperature decreases, they retain their shape and solidify again.

Step Eight: Singulation

Singulation is the final process of creating a substrate package. The process involves using a blade to cut the finished substrate strips into individual packages. Once the singulation process is complete, the packages are placed on a tray for package testing and the rest of the process steps.

The various steps involved in assembling conventional packages highlight how factors such as precise alignment, optimal electrical connections, and robust protection against external damages are integral to their formation. In the next episode, wafer-level packages—the other main type of semiconductor packages—will be explored in detail.

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The Process of Semiconductor Package Design

▲ Figure 1. Aspects of semiconductor package design (Source: Hanol Publishing)

Figure 1 displays the various aspects of semiconductor package design. The design process begins with the department responsible for the chip design providing key information, including the chip pad coordinates, chip layout, and package interconnection data. Then, based on the packaging material, the team designs the structure of the semiconductor package which consists of the substrate and the leadframe. This process involves applying design rules that consider the package’s mass production, manufacturing process, process condition, and required equipment.

The package’s feasibility should be reviewed at the beginning of development and, afterwards, given to chip and product designers for feedback. Once the feasibility study is completed, orders must be placed to system semiconductor manufacturers with design drawings of the package, tools, leadframe, and substrate. While the wafers are being delivered to be packaged, tools, leadframe materials, and substrates on top of design drawings for the connection of wires or solder bumps need to be prepared. For the package process, design drawings for wire or solder bump connections must be shared in advance with package process and manufacturing engineers.

When these design drawings are shared, package design engineers conduct a feasibility test by connecting the package solder ball layout and the chip’s pad sequence to check whether wiring is possible. Through the pre-feasibility phase, the engineers propose the package solder ball arrangement, package size, and specifications to improve the characteristics and process of the semiconductor chip and device.

Optimizing the Characteristics of the Package

▲ Figure 2. The process of package design optimization (Source: Hanol Publishing)

The package design optimization process is shown in Figure 2. The optimal pad placement is proposed in the initial stage of the package feasibility review before work is made on securing the possibility for wiring and optimizing characteristics as well as the workability of packages. To optimize these features, analyses of the structural, thermal, and electrical characteristics are performed.

Today, it is imperative to enhance all of these characteristics to meet the semiconductor industry’s increasing demands for improvements in speed, integration, and performance. In the case of electrical characteristics, solder balls are created in the package to increase the number of pins connecting the package to the PCB board and more wiring is added. As a result, the designs of board substrates, leadframes, and PCBs are becoming finer and more complex. However, there are limits when manufacturing these devices related to the process capabilities of the packaging company and the manufacturers that produce components such as the substrate. In package design, therefore, design rules concerning materials, processes, and equipment are created, reviewed periodically, and shared between chip designers and manufacturers of substrates and packages in order to prevent quality issues.

By sharing the design rules, package process engineers and process engineers from substrate manufacturers may work together to reduce the size and pitch of package solder balls in addition to the width and spacing of the signal wiring. Likewise, design rules are used to specify items that range from process capabilities to electrical specifications. Additionally, the methods of managing the tolerance¹ of the package and substrate—as well as the package’s process capabilities—are detailed in the design rules.

More specifically, the rules also manage the tolerance that satisfies the rigorous electrical specifications. To meet the electrical specifications, drawings are created based on pre-validated design data to manage and specify the tolerance of three areas in order: each high-speed signal line, the dielectric² thickness to manage the impedance³ coherency of each signal line, and the via size⁴ for an optimal low-power design. On the other hand, to improve the efficiency and mass production during the package process, the standard marking pattern is taken into account when designing devices like substrates and managed as a design rule.

¹ Tolerance: The range of errors in space or values created from the difference of work capabilities.

² Dielectric: An electrical insulator that can be polarized by applying an electric field.

³ Impedance: A measure of the extent to which a circuit opposes the flow of electricity.

⁴ Via size: The size of holes used for electrical connection between different layers of a printed circuit board.

Analyzing the Packaging Structures

Computer simulation is used to analyze semiconductor packaging structures. Typically, analysis through computer simulation involves applying the derived general equations to specific conditions in order to understand a certain phenomenon. There are four steps involved in the standard computer simulation process.

First, factors that govern a natural phenomenon and the relationship between the factors are placed in mathematical expressions such as the governing equation⁵, and then the phenomenon that is the subject of analysis is modeled so that it can undergo computer simulation. Next, the governing equation is applied to the model to calculate it mathematically, and, finally, the result is applied to the phenomenon to analyze it. The methods of analysis through computer simulation are mainly divided into the finite difference method, finite element method (FEM), and finite volume method. FEM is most widely used to analyze semiconductor structures. The engineering aspect of FEM refers to its ability to convert infinite number of points and degrees of freedom⁶ into finite number of points and degrees of freedom. These points are then computed as linear system of equations.

⁵ Governing equation: The mathematical formulae that form the basis of a computational code. For computational modeling, they govern the predicted behavior of fluids in the subsurface provided by the code.

⁶ Degrees of freedom: The number of values in the final calculation of a statistic that are free to vary.

FEM is composed of a finite number of building blocks called elements. Each element has a finite number of points and a governing equation, while a value is obtained by solving the equation. To understand structural analysis, it is essential to understand three key properties of materials that are required for such analysis: coefficient of thermal expansion (CTE), Poisson’s ratio, and stress.

CTE is a property which describes the extent a material changes in length due to fluctuations in temperature. In general, a material expands as the temperature increases and it contracts as the temperature decreases. CTE is therefore defined as the fractional increase in the length of a material per unit rise in temperature. Meanwhile, Poisson’s ratio is the expansion or contraction of a material in directions perpendicular to the specific direction of loading. To understand this ratio, it is helpful to consider the effect of pushing and pulling on an object. If you pull on an object lengthwise from both ends and apply a tensile force, it stretches in the direction of its length and contracts in the direction of its width. However, if you push it from both ends lengthwise and apply a compressive force, it will shrink in the direction of the force and stretch in the direction of its width. Lastly, stress is the internal force created within an object to resist an external force while maintaining its shape. It is measured in units of pressure.

These material properties are applied to the three main areas of structural analysis utilized in semiconductor packages: package warpage, solder joint reliability, and package strength.

Warpage Analysis

When the temperature rises and goes back down to room temperature during the packaging process, the CTE between dissimilar materials may differ and cause the package to warp and create defects. Therefore, structurally analyzing the package based on the product structure, the material’s elastic modulus⁷, the CTE, the process temperature, and time, makes it possible to predict warpage and prevent defects from occurring.

⁷ Elastic modulus: A value that represents the stiffness of a material in solid mechanics. It is defined as the ratio of stress and strain.

Solder Joint Reliability

Solders serve as mechanical and electrical connections between the semiconductor package and the PCB substrate. As the reliability of solder joints is very important, the joints should undergo structural analysis before a package is made in order to improve the package structure and materials.

Failure mechanisms in solders are primarily a combination of shear cracking caused by in-plane shrinkage and tensile cracking caused by axial tension. Therefore, structural analysis of solder joints is performed by analyzing the amount of stress applied to the solder joint under various process or usage conditions.

Strength Analysis

As the package serves to protect the chip from external forces, the chip’s robustness to external impacts is represented by the package strength. To determine the robustness of a package, a universal testing machine (UTM)⁸ is used to perform three-point bending or four-point bending which calculate the breaking strength. Structural analysis simulates these UTM tests to deduce the stress levels in each area of the package and uses the breaking strength of a specific material as a reference to predict the breaking strength of the whole product.

⁸ Universal testing machine (UTM): A tester that measures the strength of a material by pulling or compressing a material with a set weight to measure its tensile, flexural, and compressive strengths.

Heat Interpretation

Electronic devices consume power and generate heat as they operate. This heat raises the temperature of components that include semiconductor products, which can compromise the functionality, reliability, and safety of electronic equipment. Therefore, electronic equipment must have proper cooling systems to keep the temperature of components below a certain level in any environment.

Thermal analysis, thus, becomes an essential test as heat dissipation is one of the crucial roles of semiconductor packages. Therefore, generated heat, the heat dissipation effect of the package material and structure, and the temperature effect when the semiconductor package is applied to the system must be accurately understood in advance to be reflected in the package design.

▲ Figure 3. Key temperature points of the package (Source: Hanol Publishing)

In order to perform and utilize thermal analysis on a semiconductor package, it is necessary to define the key temperature points on the package. The main temperature points of the package are ambient temperature (Ta), junction temperature (Tj), case temperature (Tc), and board temperature (Tb). The temperature for package specifications is usually either Tj max. or Tc max., terms which refer to the maximum temperature that ensures the semiconductor device operates normally. Figure 3 shows each temperature point in the schematic diagram of a package.

▲ Figure 4. Types of heat characteristics in packages (Source: Hanol Publishing)

By using the main temperature points of the package, it becomes possible to calculate thermal resistance—the most important characteristic for heat protection. Package thermal resistance is an index expressed in units of ℃/W which identifies the temperature increase of a semiconductor product in relation to the surrounding temperature when 1 watt of heat is generated by the chip. This ratio changes according to each product and the environmental conditions. Common types of thermal resistance include junction-to-ambient (Ja), junction-to-board (Jb), and junction-to-case (Jc), and they reveal indications such as the package’s resistance and immunity to heat.

Electrical Simulation

▲ Figure 5. An example of a packaged RLGC model (Source: Hanol Publishing)

As semiconductor chips become faster and denser, packages also have a significant impact on the characteristics of semiconductor products. In particular, when a high-performance semiconductor chip is packaged, accurate electrical simulation of the package state is essential. To predict the electrical problems arising from the complex wiring of high-performance semiconductor chips, modeling such as RLGC is used. Thus, electrical simulation creates models and uses them to predict the timing of data transmission, the signal quality, and the shape accuracy in high-speed digital systems.

The basic elements of an electrical model for the electrical analysis of a package are resistance, inductance, and capacitance. Just strong enough to obstruct the flow of a current, resistance is inversely proportional to the unit current flowing on an object. Inductance is the ratio of counter electromotive force that forms from electromagnetic induction caused by a change in the current flowing in a circuit. Finally, as the physical quantity that shows how much charge can be stored, capacitance is the charge stored by a capacitor at unit voltage.

▲ Figure 6. Areas of electrical analysis (Source: Hanol Publishing)

Using modeling such as RLGC, it becomes possible to predict the most important characteristics, namely signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) as shown in Figure 5. SI is the measure of an electrical signal’s quality, while PI measures the power transmission’s quality. Lastly, EMI is an electromagnetic disturbance where radiated or conducted electromagnetic waves interfere with the functioning of other devices. Thus, noise problems should be checked in advance to minimize the developing period and ensure that the integrity and power delivery system can support the creation of a reliable board. SI, PI, and EMI have a close and organic relationship with each other, so a comprehensive design that considers all three is essential for electrical analysis.

Supporting the Advancement of Semiconductors

No matter how much individual chip performances improve, the overall system performance cannot be guaranteed unless the electromagnetic characteristics of the pathways connecting the chips on the package and the power supply grid are properly managed. The package design process and related analyses are therefore vital to ensuring the operation and continued advancement of chips. By following certain design rules, it is possible to create the blueprint for semiconductor packages with optimal characteristics. This optimization of a package’s characteristics is then realized through structural, thermal and electrical analyses. Ultimately, these stages of design and analysis make it possible to meet the increasing demands for improvements in semiconductors’ speed, integration, and performance.

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Stacked Packages

Imagine a housing complex consisting of numerous low-rise buildings for thousands of people. It would require a very large area to accommodate the residents. However, the same number of residents could fit in a single skyscraper. This example clearly shows one of the key benefits of stacked packages. Compared to a product made with multiple packages spread horizontally across a wide area, a product consisting of stacked packages offers enhanced performance within a much smaller space. In addition to being an important packaging technology, stacked packaging is also an essential method in product development.

It used to be common for products to have only one chip per package, but it is now possible to develop a multi-chip package that has different functions or to place multiple memory chips in a single package that has an increased capacity. Furthermore, the development of SiP has allowed various system components to be implemented in a single package. Such technologies have enabled semiconductor companies to create high value-added products while also responding to the diverse needs of the market.

▲ Figure 1. Different methods of stacking packages (Source: Hanol Publishing)

As Figure 1 shows, stacked packages are categorized into three major types based on their distinct development techniques: 1) package stacks that are made by vertically stacking the packages, 2) chip stack packages that use wire bonding to stack chips within a single package, and 3) chip stack packages that use through-silicon via (TSV)¹ rather than traditional wire bonding for the internal electrical interconnections. Each of these stacked packages has different features and various advantages and limitations which will determine their future applications.

¹Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

#1. Package Stacks

A package stack is made by vertically stacking the packages. Consequently, its advantages and disadvantages are opposite to that of chip stack packages. The package stack method places packages on top of each other once they have completed testing, so it is possible to easily replace a package that fails a test with a properly functioning package. This, in turn, results in better test yields compared to chip stack packages. However, due to package stacks’ larger size and longer signal paths, their electrical characteristics can be inferior to that of chip stack packages.

One of the most common package stacking methods is package-on-package (PoP), which is widely used in mobile devices. For a PoP in a mobile device, the types and functions of the chips used in the upper and lower packages may vary while the chip manufacturers can also differ.

In general, the upper packages mainly include memory chips made by semiconductor memory companies while the packages stacked below feature chips with a mobile processor that are designed by fabless companies and produced in foundries and Outsourced Semiconductor Assembly and Test (OSAT) facilities. As the packages are manufactured by different parties, quality testing is conducted before being stacked. Even if a defect occurs after stacking, it can be reworked by just replacing the defective part with a new package. Accordingly, it is clear that the mobile business sees significant benefits from package stacking.

#2. Chip Stacks with Wire Bonding

When placing multiple chips in a package, they can either be stacked vertically or attached horizontally to the board. Given that the horizontal layout may result in a larger package size, vertical stacking has become the preferred method. Compared to package stacks, chip stack packages are smaller in size and possess enhanced electrical characteristics due to their shorter electrical signal paths. However, even if a defect is found in a single chip during testing, the entire package needs to be discarded. Thus, chip stack packages have relatively low test yield rates.

In chip stack packages, the memory capacity increases as more chips are stacked in the package. This has resulted in the development of technologies which enable more chips to be layered in a package. However, as it is undesirable for the package to get thicker even as more chips are stacked, technologies that limit the package’s thickness have been under development. To do so, everything that affects the thickness of a package including the chip and the substrate must be made thinner, and the gap between the uppermost chip and the surface above the package needs to be reduced. This poses many challenges in the packaging process because chips are more likely to get damaged as they become thinner. That is why developments in packaging processes are underway to overcome these challenges.

#3. Chip Stacks with TSV

TSV is a chip stacking technique that drills holes through silicon to accommodate electrodes. Instead of using the traditional method of wiring to connect chip-to-chip or chip-to-substrate, TSV connects chips vertically by drilling holes in the chip and filling them with conductive materials such as metal. Although a chip-level process is used when stacking with TSV, a wafer-level process is used to form TSV and solder bumps on the front and back of the chip. Therefore, TSV is classified as a wafer-level package technology.

▲ Figure 2. A cross-sectional view of a chip which applied TSV technology (Source: Hanol Publishing)

The main advantages of packages using TSV are the high level of performance and smaller package size. As shown in Figure 2, the chip stack package with wire bonding has wires connected to the sides of each stacked chip. As there are more stacked chips and connected pins, the wiring becomes more complex, with more space needed to connect them. In contrast, the chip stack with TSV does not require complicated wiring and, therefore, allows reduction in package size.

As explained in the previous episode, flip chips have good electrical properties due to several reasons: it is easier to form I/O pins in desired locations, there is an increase in the number of pins, and they have short electrical signal transmission paths. These are the same reasons that give TSV packages strong electrical properties. When sending an electrical signal from a chip to the chip right below it, TSV allows the signal to go straight down. In contrast, if wire bonding is used, the signal transmission path becomes much longer as the signal has to go down to the substrate before making its way up to the chip. As shown in the image of a chip stack with wiring in Figure 2, wiring connections cannot be made in the center of the chip. Contrastingly, TSV packages allow the center of the chip to be drilled, made into electrodes, and connected with other chips. Unlike wiring connections, TSV enables the number of pins to be significantly increased.

High Bandwidth Memory (HBM) utilizes a new DRAM architecture that takes advantage of this ability to increase the number of pins. Typically, an “X4” in DRAM specification implies that there are four pins that can send information, or 4 bits of information can be simultaneously sent from the DRAM. Accordingly, X8 refers to 8 bits, X16 refers to 16 bits, and so on. It is favorable to increase the number of these pins as it allows more information to be sent simultaneously. However, chip stacking with wiring could only reach X32 due to limitations, while stacking through TSV does not have such limitations, enabling HBM to go up to X1,024.

Current mass-produced memory products that apply TSV to DRAM include HBM and 3D stacked memory (3DS). The former is used in graphics, networking, and high-performance computing (HPC) applications, while the latter is primarily used as a DRAM memory module.

▲ Figure 3. A 2.5D package using HBM (Source: Hanol Publishing)

Rather than being a fully packaged product, HBM is a semi-packaged product. When an HBM product is sent to a system semiconductor manufacturer, they use an interposer² to make a 2.5D package³, with an HBM placed side-by-side to a logic chip as shown in Figure 3. Since substrates in 2.5D packages are unable to provide pads that can support all the I/O pins of both HBMs and logic chips, interposers come in to accommodate HBMs and logic chips by creating pads and metal wiring. Then, these interposers connect back with the substrate. As for these 2.5D packages, they are considered as a type of SiP.

3DS memory, another product that uses TSV, is a type of memory module with a BGA⁴ package mounted on a PCB board. Although DRAM memory modules in servers require high speed and a large capacity, chip stack packages that use wiring are unable to meet these requirements due to their speed limitations. This has led to the use of modules made from TSV-applied chip stack packages for high-end systems such as servers.

²Interposer: Wide and extremely fast electrical signal conduits used between die in a 2.5D configuration.

³2.5D package: 2.5D and 3D packages include multiple integrated circuits inside each package. In the 2.5D structure, two or more active semiconductor chips are placed side-by-side on a silicon interposer. In the 3D structure, active chips are integrated by die stacking vertically.

⁴Ball grid array (BGA): A type of surface mount chip package that uses a grid of solder balls as its connectors.

System-In-Package (SiP)

A package consisting of HBM and a logic chip is a type of SiP. As its name suggests, SiP implements a system in a single package. While components such as sensors, analog-to-digital (A/D) converters, logic chips, memory chips, batteries, and antennas must also be included to form a complete system, it is not possible to include all these system components into a single package with the current developments in technology. It has therefore become the goal of researchers to continue developing package technologies in this area, and SiPs today usually refer to combining some of the system components in a single package. For instance, packages that have applied HBM combine HBM and the logic chip into a single package to create an SiP.

Unlike SiP, system-on-chip (SoC) implements system functions on the chip-level. In other words, several system functions are implemented on one chip. As an example, most processors today have static RAM (SRAM) memory within the chip, allowing the logic functions of the processor and the memory functions of the SRAM to be implemented together on a single chip. Therefore, these processors are classified as an SoC.

SoCs have a complex and lengthy development process because they require multiple functions to be packed into a single chip. Moreover, upgrading the functions of a single element in an already developed SoCs requires one to design and develop them from scratch. SiPs, on the other hand, are easier and quicker to develop because they are made by collecting already developed chips and devices into a single package. Even if the device has a completely different structure, the chip itself is developed and manufactured separately, making it relatively easy to make it into a single package. Also, if just a single aspect of the function needs an upgrade, the newly developed device can be implemented in the chip without developing the whole package from scratch. However, if a product is going to be used in large quantities over an extended period of time, it may be more efficient to develop it as an SoC rather than an SiP as the latter requires more materials to be manufactured and leads to a larger package size to fit multiple chips in a single package.

Despite the various differences between SoCs and SiPs, it is not necessary to choose between one of these two technologies. In fact, they can be combined to create synergies. Once an SoC is developed, it can be packaged with other functional chips into a single package and implemented as an enhanced SiP.

▲ Figure 4. Comparison of signal transmission path length of SoC and SiP stacked with TSV (Source: Hanol Publishing)

When comparing the performance of SiPs and SoCs, it was originally thought that the electrical characteristics of SoCs were better due to their implementation on a single chip. However, with the advent of chip stacking technology such as TSV, SiPs can have electrical characteristics that are on par with SoCs. Figure 4 shows a comparison of the signal transmission paths of SoCs and SiPs stacked with TSV. When a signal is transmitted from one end of an SoC chip to the opposite corner, the path is much shorter if the SoC is divided into nine parts and stacked with TSV.

▲ Figure 5. Conceptual diagram of a chiplet

In addition to a focus on the various advantages of SiPs stacked with TSV, a technology called chiplets has gained a lot of attention recently. As shown in Figure 5, it is a technology that divides existing logic chips by function and connects them with TSV. Chiplets have three main advantages over monolithic chips.

First, the chiplets offer a yield improvement over monolithic chips. The wafer yield is limited if the size of a single chip on the wafer is big, but making the chips smaller can increase wafer yield and thus reduce manufacturing costs. Take the example of a 300 mm wafer cut into 100 or 1,000 chips (net die). If the wafer process causes five chips to fail because five impurities are evenly distributed across the front of the wafer, the product with 100 chips has a yield of 95% and the product with 1,000 chips has a yield of 99.5%. The yield is therefore much higher for products with more net dies, or with a smaller chip size. Therefore, it is more cost-effective to cut up a chip by functions and implement it as SiP rather than as a single chip through SoC.

The second advantage is streamlined development. With a single chip, the entire chip needs to be redeveloped in order to upgrade its functionality or apply the latest technology. However, dividing the chips can shorten the development period and make the process more efficient as only the chip with the relevant function needs to be upgraded or developed with the latest technology. For example, some of the segmented chips use the existing 20 nanometer (nm) technology, while others use the latest sub-10 nm technology to increase development efficiency.

The third benefit is the centralization of technological development. By dividing chips by function, it is not necessary to develop a chip for every function. Only the chips used for the core technology need to be developed, and everything else can be purchased or outsourced so companies can focus on developing their own core technologies.

Thanks to these advantages, major semiconductor companies are introducing chiplet-based semiconductor products or have added them to their roadmaps.

Following the previous episode that looked into the various conventional and wafer-level packaging technologies, we finished the roundup of packaging technologies and their distinct characteristics. While stacked packages and SiPs have come a long way in their development, semiconductor researchers will continue efforts to enhance the capability of these high-quality technologies with numerous functions that take up a minimal amount of space. These efforts are expected to increase the efficiency of the packaging process as a whole through the production of packages with advantages in size, functionality, and performance.

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The post Semiconductor Back-End Process Episode 4: Understanding the Different Types of Semiconductor Packages, Part 2 first appeared on SK hynix Newsroom.

Classification of Semiconductor Packages

Figure 1 shows the various types of semiconductor packages broken down into two main categories: conventional and wafer-level packaging. In conventional packaging, the wafer is sawed before the chip is packaged, while wafer-level packaging involves a part, or all, of the packaging process being performed at the wafer level before proceeding with wafer sawing.

▲ Figure 1. Types of semiconductor packages (Source: Hanol Publishing)

Based on the materials being packaged, conventional packages can be divided into ceramic and plastic packaging. Plastic packages can be further categorized into leadframe or substrate packages depending on the medium of the package.

As for wafer-level packages, they can be categorized into four different types: 1) wafer-level chip scale packages (WLCSP) in which wiring and solder balls are formed on top of the wafer without a substrate 2) redistribution layers (RDL) that use a wafer-level process to rearrange the pads¹ on the chip that are electrically connected to the outside 3) flip chip packages in which solder bumps² are formed on the wafer to undergo the packaging process, and lastly 4) through-silicon via (TSV) packages that utilize TSV to make internal connections within stacked chips.

For WLCSP, it is divided into fan-in and fan-out WLCSP. The process for fan-in WLCSP involves attaching wiring and solder balls on top of the wafer, while fan-out WLSCP involves rearranging the chips into a molding³ wafer. This is done to form wiring through a wafer-level process and to attach solder balls onto a package larger than the chip.

¹Pad: A passageway that electrically connects to other mediums. On a chip, pads are made to electrically connect with the outside through wires or flip chip bumps. On a substrate, pads are made to connect the chips to each other.
²Solder bump: A conductive bump that connects a chip to a substrate through flip chip bonding. It also connects ball grid arrays (BGA) or chip scale packages (CSP) to a circuit board.
³Molding: The process of sealing wire-bonded or flip chip bonded semiconductor products with an epoxy molding compound (EMC).

Conventional Packages

Plastic Packages: Leadframe

▲ Figure 2. Types of leadframe packages (Source: Hanol Publishing)

In a plastic package, the chip is covered in plastic materials such as epoxy mold compound (EMC)⁴. A leadframe package is a type of plastic package that uses a metal lead called a leadframe as its substrate. The leadframe uses an etching method to form wiring on thin metal plates.

⁴Epoxy mold compound (EMC): A thermosetting plastic with excellent mechanical and electrical insulation in addition to temperature resistance properties. It is a resin with relatively small molecular weight capable of three-dimensional curing in the presence of a curing agent or catalyst.

Figure 2 shows the different types of leadframe packages. In the 1970s, through hole types like dual in-line packages (DIP) or zig-zag in-line packages (ZIP) in which leads are inserted into holes in the printed circuit board (PCB) were commonly used. Later, as the number of pins increased and the design of PCBs became more complex, techniques inserting leads into holes started to reach their limitations. This eventually led to the development of surface-mounting types such as thin small outline packages (TSOP), quad flat packages (QFP), and small outline J-leaded packages (SOJ). For products that require a large number of I/O pins like logic chips, packages like QFP in which leads are attached on all four sides are applied. Packages such as thin QFP (TQFP) and TSOP were also developed as system environments required thinner packages.

As higher speeds became more important for semiconductor products, substrate packages which can support multi-layer wiring designs became the mainstream packaging technology. Nevertheless, leadframe packages such as TSOP are still widely used because of their low manufacturing costs. Since leadframes are made by stamping or etching wiring shapes on metal plates, they are cheaper than substrates that have a relatively complex manufacturing process. Therefore, leadframe packages are still the preferred choice for the production of semiconductor products that do not require high-speed electrical characteristics.

Plastic Packages: Substrate

As the name suggests, substrate packages use a substrate as the medium. They are sometimes referred to as laminated packages because the substrate is made using multiple layers of film. Unlike leadframe packages which only have one metal layer in the wiring as they are made with a leadframe—a metal plate unable to form more than two metal layers—substrate packages can feature several layers of wiring. This leads to better electrical characteristics and a smaller package size. Another key difference between leadframe and substrate packages is the wiring connection process. The wiring connecting the chip and the system must be separately implemented on the leadframe and the substrate. If the wiring needs to cross each other, a substrate can make a wire cross to another metal layer while a leadframe is unable to do this as it only has one metal layer.

As shown in Figure 3, substrate packages can also feature a large number of pins by arranging the solder balls that serve as the pins on one entire side. In contrast, the leads acting as pins of leadframe packages can only be formed on the edges of one side. This also improves the electrical characteristics of substrate packages in the process. As for the size of the packages, leadframe packages are generally larger as they consist of the main frame and the space taken up by the lead on the sides. However, substrate packages are smaller as the pins are on the bottom of the package to save space.

▲ Figure 3. Comparison of BGA and LGA (Source: Hanol Publishing)

Due to these advantages, most semiconductor packages today are substrate types. The most common type of substrate package is the ball grid array (BGA) package, but land grid array (LGA) packages, which feature a ball land structure consisting of flat contacts instead of balls as seen in Figure 3, have also been used in recent times.

Ceramic Packages

Ceramic packages have a ceramic body which provides excellent heat dissipation and reliability. However, as the process of manufacturing ceramics is expensive, the overall cost of manufacturing the packages is also high. Consequently, these packages are mainly used for logic semiconductors that require high reliability as well as for verifying packages made for CMOS image sensors (CIS).

Wafer-Level Packages

Fan-In WLCSP

WLCSP is a prime example of a wafer-level package as most of the manufacturing process takes place at the wafer level. In a broader sense, however, any package that is even partially processed at the wafer level is considered a wafer-level package. Examples include packages that use RDL, flip chip technology, and TSV. In regards to fan-in WLCSP and fan-out WLCSP, the term “fan” refers to the chip’s size. A fan-in WLCSP has package wiring, an insulation layer, and solder balls directly on top of the wafer, contributing to various advantages and disadvantages when compared to conventional packages.

As the size of the package is equal to the size of the chip in fan-in WLCSP packages, they can be manufactured to the smallest dimensions. Furthermore, as the solder balls are directly attached to the chip without a medium such as a substrate, the electrical transmission path is relatively short and, thus, improves electrical characteristics. Lastly, these packages can be processed at a low cost as there is no need for package materials such as substrates and wires. As the package is processed all at once at the wafer level, it can further save costs if there is a large number of net dies—the chips on the wafer—and a high yield.

As for the downsides, fan-in WLCSP packages have weak physical and chemical protection capabilities due to the silicon (Si) chip acting as the package itself. For this same reason, these packages’ coefficient of thermal expansion⁵ is vastly different to the PCB substrate to which they will be attached. This puts more stress on the solder balls connecting the two and makes solder joint reliability⁶ relatively weak.

⁵Coefficient of thermal expansion: The rate at which the volume of an object increases with rising temperature due to constant pressure. The expansion or contraction is linearly related to the increase or decrease in temperature.
⁶Solder joint reliability: The quality that ensures the joint can conduct its intended purpose of making a mechanical and electrical connection during the life of the package when it is connected to a PCB with soldering.

Another disadvantage of fan-in WLCSP packages is the inability to use existing infrastructure for package testing. And if the package ball layout is larger than the chip size, packaging is not possible at all as the solder ball layout cannot be made on a package. Finally, the packaging costs for fan-in WLCSP can be higher than conventional packaging if the number of chips on the wafer is small and the yield is low.

Fan-Out WLCSP

Fan-out WLCSP possesses the advantages of fan-in WLCSP while overcoming its disadvantages. Figure 4 shows this comparison between fan-in and fan-out WLCSP.

▲ Figure 4. Comparison of fan-in WLCSP and fan-out WLCSP (Source: Hanol Publishing)

In a fan-in WLCSP, all of the solder balls for the package are on the chip’s surface, while a fan-out WLCSP features solder balls for the package which can be “fanned out” away from the chip. For fan-in WLCSP, the wafer is sawed after the packaging process is complete rather than in the middle of the process. Consequently, the size of the chip and the package must be the same, and the solder balls must be within the chip’s size. Fan-out WLCSP, on the other hand, involves sawing the chips before the packaging process and arranging the sawed chips on a carrier to reshape the wafer. During this time, the space between the chips is filled with EMC to form a wafer. The wafers are then removed from the carrier, subjected to wafer-level processing, and sawed to make a unit of fan-out WLCSP.

In addition to offering good electrical characteristics just like fan-in WLCSP, fan-out WLCSP overcomes several disadvantages of fan-in WLCSP. These include the inability to use existing infrastructure for package testing, the inability to package products when the ball layout is larger than the chip’s size, and increased processing costs arising from the need to package defective chips all together. Due to these advantages of fan-out WLCSP, the application of these packages has been growing in recent years.

RDL

RDL technology refers to the act of rewiring. The purpose of this technology is to rearrange the bonding pads that are already formed on the wafer by adding additional metal layers. Figure 5 shows a diagram and a cross-sectional structure of a center pad chip in which the pads have been redistributed to the edges using RDL technology. RDL technology is a wafer-level process that only reconfigures the pads, and the wafers that have gone through RDL undergo a conventional packaging process to complete the package.

▲ Figure 5. A cross-sectional view of a chip with RDL technology (Source: Hanol Publishing)

When a customer requests a unique pad arrangement on a wafer, it is more efficient to rearrange the pads on an existing wafer using RDL technology during its packaging rather than going through a new wafer fabrication process. Additionally, RDL technology is also used for chip stacking of center pad chips.

Flip Chip

Flip chip technology gets its name because the bumps formed on the chip are flipped and attached to the package body such as a substrate. It is an interconnection method that electrically connects chips and boards such as substrates, just like traditional wire bonding.

Flip chip technology has mostly replaced wire bonding, however, due to its superior electrical properties. There are two reasons for this: I/O pins that can be electrically connected are not as limited in number or placement as in wire bonding, and the electrical signal transmission path is also shorter compared to wire bonding.

The placement of metal pads on top of a chip used in wire bonding is one-dimensional, limiting their placement to the edges or center of a chip. Flip chip bonding, on the other hand, has no process constraints when it is bonded to the substrate and when the solder bumps are formed. So, the metal pad can be arranged in a two-dimensional manner by using a whole entire side of the chip, which increases the number of metal pads by the power of two. In addition, the pads that will form the bumps can be placed anywhere on top of the chip. Moreover, pads that supply power can be placed near areas where power is required, further enhancing the electrical characteristics. As Figure 6 shows, the signal path for flip chip bonding becomes much shorter compared to wire bonding when exporting information from the chip to the same package ball. It further boosts the electrical characteristics.

▲ Figure 6. Comparison of signal transmission paths for wire bonding and flip chip bonding (Souce: Hanol Publishing)

As explained, WLCSP and flip chip both form solder balls on top of a wafer. Although both technologies can be mounted directly on a PCB board, there is a fundamental difference between the two—the size of the solder.

With WLCSP, the diameter of its solder balls is typically a few hundred micrometers (μm), but the solders formed on the flip chip are only a couple dozens of μm. Due to its small size, the solder formed on the flip chip is often referred to as a solder bump rather than a solder ball and it is difficult to ensure solder joint reliability with this solder alone. WLCSP solder balls can handle the stress from the difference in the coefficient of thermal expansion between the substrate and the chip. Flip chip solder bumps, on the other hand, cannot. Therefore, to ensure solder joint reliability, a polymer-type underfill material must be used to fill between the flip chip bumps. The underfill material disperses the stress on the bumps and ensures solder joint reliability.

As there are a wide variety of semiconductor package types in addition to the ones explained in this article, the next episode will put a special focus on stack packages and system-in-packages, while subcategories such as wire bonding and TSV will also be explained.

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The post Semiconductor Back-End Process Episode 3: Understanding the Different Types of Semiconductor Packages first appeared on SK hynix Newsroom.