Smaller. Faster. Higher bandwidth. Better performance. Today’s leading memory products are rapidly evolving to meet the intense demands of the AI era. However, these advancements bring with them a challenge which can hinder the development of next-generation products—excessive heat generation.

To tackle this issue, SK hynix made an unprecedented breakthrough by developing a new and innovative packaging technology called MR-MUF¹ that improves heat dissipation in chips. Applied to the company’s groundbreaking HBM² products since 2019, MR-MUF has set SK hynix aside from the competition. As the only company to use MR-MUF and having received excellent client evaluations for the heat dissipation characteristics of its HBM products which apply the technology, SK hynix has risen to the position of HBM market leader.

¹Mass reflow-molded underfill (MR-MUF): Mass reflow is a technology that connects chips together by melting the bumps between stacked chips. Molded underfill fills the gaps between stacked chips with protective material to increase durability and heat dissipation. Combining the reflow and molding process, MR-MUF attaches semiconductor chips to circuits and fills the space between chips and the bump gap with a material called liquid epoxy molding compound (EMC).
²High Bandwidth Memory (HBM): A high-value, high-performance product that possesses much higher data processing speeds compared to existing DRAMs by vertically connecting multiple DRAMs with through-silicon via (TSV).

This Rulebreakers’ Revolutions episode will look at how the pioneering development of MR-MUF, particularly its new materials with high thermal conductivity, solved the problem of excessive heat generation in next-generation HBM products.

The Mission: Overcome the Problem of Heat Generation

As memory products evolve, heat generation becomes an increasingly pressing issue for several reasons. For example, the miniaturization of semiconductors negatively impacts heat dissipation due to the reduced surface area and increased power density. In the case of stacked DRAM products such as HBM, thermal resistance increases due to the longer heat transfer paths, while thermal conductivity is limited by the materials between chips. Moreover, the continuous advancements in speed and capacity result in increased heat generation.

The inability to sufficiently control heat in semiconductor chips can negatively impact a product’s performance, lifecycle, and functionality. This can become a serious concern for customers and significantly impact factors including productivity, energy costs, and competitiveness. Consequently, heat dissipation, along with capacity and bandwidth, has become a key consideration during the development of advanced memory products.

Attention has therefore turned to semiconductor packaging technology as one of its main functions is heat control. Up until the second generation of HBM, HBM2, SK hynix applied the industry-standard TC-NCF³ process to its HBM products. However, with advancements in HBM that required chips to become thinner to accommodate additional chip layers, the applied packaging technology needed to control higher levels of heat and pressure. Issues such as chip warpage due to pressure and thickness limitations in densely stacked products also needed to be addressed as SK hynix planned to develop its next-generation products. At this point, the company needed to think outside the box by developing a new packaging technology for its future products.

³Thermal compression non-conductive film (TC-NCF): A method of stacking chips by applying a film-like substance between chips. Heat and pressure are applied to melt the substance so chips are glued together.

MR-MUF & Its New Materials: The Missing Pieces to the Heat Control Puzzle

As SK hynix was developing HBM2E, the third generation of HBM, controlling heat became a major focal point for improvement. Even when TC-NCF was being recognized as a packaging solution suitable for densely stacked products, SK hynix challenged the status quo and strove to develop a new packaging technology offering improved heat dissipation. After countless tests and trials, the company unveiled its new packaging technology MR-MUF in 2019 which would change the future of the HBM market.

The structural difference between TC-NCF and MR-MUF that influence heat dissipation

Developed by multiple teams at SK hynix, MR-MUF heats and interconnects all the vertically stacked chips in HBM products at once. This makes it more efficient than TC-NCF which applies a film-type material after each chip is stacked. Moreover, MR-MUF increases the number of thermal dummy bumps—which are effective at dispersing heat—by up to four times compared to TC-NCF.

Another important feature of MR-MUF is the addition of a protective material called EMC⁴ used to fill the spaces between chips. A thermosetting polymer with excellent mechanical and electrical insulation as well as heat resistance, EMC addressed the need for high environmental reliability and control over chip warpage. Due to the application of MR-MUF, HBM2E improved heat dissipation performance by 36% compared to its predecessor, HBM2.

⁴Epoxy molding compound (EMC): A heat dissipation material based on epoxy resin, a type of thermosetting polymer, that seals semiconductor chips to protect them from environmental factors such as heat, moisture, and shock.

Although MR-MUF was also used for HBM2E’s successor, the 8-layer HBM3, SK hynix elevated the MR-MUF process to another level when developing the 12-layer HBM3 in 2023. As the DRAM chips had to be 40% thinner than the chips used in the 8-layer HBM3 in order to maintain the product’s overall thickness, chip warpage became a significant issue. SK hynix actively responded by developing Advanced MR-MUF, introducing the industry’s first chip control technology⁵ and new protective materials that improved heat dissipation. In this process, SK hynix once again achieved innovation in materials as the new EMC applied in Advanced MR-MUF offered a 1.6-time improvement in heat dissipation properties compared to the EMC for the original MR-MUF.

⁵Chip control technology: The application of a momentary burst of high heat to each chip as it is stacked, causing the bump under the top chip to fuse to a thin pad on top of the bottom chip. The pad holds the chip together and protects it from warpage.

With Heat Control, SK hynix Mass-Produces Highest Level of HBM

A timeline of HBM’s multiple generations and progress in heat dissipation

Starting with the development of HBM2E, the application of MR-MUF and the subsequent Advanced MR-MUF enabled SK hynix to produce the industry’s highest standards of HBM products. Fast-forward to 2024, SK hynix became the first company to mass-produce HBM3E, the latest HBM product which boasts the highest standards of performance. HBM3E saw a 10% improvement in heat-dissipation performance compared with its previous generation, the 8-layer HBM3, following the application of Advanced MR-MUF to become the in-demand memory product in the AI era. Looking ahead, the company is set to maintain its HBM leadership as it has announced plans to bring forward the mass production of the next-generation HBM4 to 2025.

Rulebreaker Interview: Kyoung-Moo Harr, HBM Package Product

To find out more about the original approach which led to the development of MR-MUF and advancement of HBM, the SK hynix newsroom spoke with Technical Leader Kyoung-moo Harr of HBM Package Product. Having actively supported the development of MR-MUF through exploration, testing, and verification of new materials, Harr discusses the impact of this innovative process.

<Other articles from this series>

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

The post [Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights first appeared on SK hynix Newsroom.

In this EE Times article, Ki-ill Moon, the head of PKG Technology Development at SK hynix, covers the evolution of packaging technology and highlights some of the company’s recent efforts and accomplishments in helping to advance the field.

As the speed, density, and functions of a semiconductor product vary depending on how the interconnection is made, interconnection methods during the packaging process are constantly changing and developing as mentioned by Moon in his previous article.

More specifically, the following four types of interconnection techniques have gradually developed over time to eventually provide more efficient and high-quality packaging techniques: wire bonding, flip chip bonding, through-silicon via¹ (TSV) bonding, and hybrid bonding with chiplets.

¹Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

With traditional wire bonding technology advancing all the way to the more recent hybrid bonding with chiplets, unprecedented achievements have been made through improvements in the package’s cost-effectiveness, operating speed, flexibility of chip design, thermal dissipation, and size reduction.

Following such developments, SK hynix developed the world’s first-ever 12-layer HBM3 in April 2023. Furthermore, the company plans to use the most high-powered packaging solution to develop hybrid bonding so it can be applied to its future HBM products such as the 16-layer HBM.

To find out more about the technologies that will help SK hynix elevate its packaging technologies and platform solutions to unprecedented levels, read the full EE Times article here: The Role of Interconnection in the Evolution of Advanced Packaging Technology

The post The Role of Interconnection in the Evolution of Advanced Packaging Technology first appeared on SK hynix Newsroom.

In this second article of our back-end process series, we will explain the different levels, diverse roles, and evolution of packaging technology.

The Four Levels of the Semiconductor Packaging Process

Electronic packaging technology is related to the hardware structure of devices. These hardware structures consist of active elements¹ such as semiconductors and passive elements² including resistors and capacitors³. Accordingly, electronic packaging is a very broad technology that can be categorized into four different levels that range from level 0 to level 3 packaging. Figure 1 shows the whole semiconductor packaging process starting from level 0 packaging which consists of detaching chips through wafer sawing. This is followed by level 1 packaging which is essentially chip-level packaging. Next, level 2 packaging mounts the chip on a module or a card before level 3 packaging equips a card that is mounted with the chip and the module to a system board. In a broad sense, this entire process is commonly referred to as “packaging” or “assembly.” In the semiconductor industry, however, semiconductor packaging generally only refers to the process of wafer sawing and chip-level packaging.

¹Active element: A device that performs a function due to the circuit implementation, just like a semiconductor memory or a logic semiconductor.

² Passive element: A device that does not have an active function such as amplification or conversion of electrical energy.

³ Capacitor: An element that stores electrons and, consequently, provides electrical capacity.

▲ Figure 1. The packaging levels of a semiconductor (Source: Principle of Electronic Packaging, p. 5)

The package generally takes the form of either the fine-pitch ball grid array (FBGA) or the thin small outline package (TSOP) as shown in Figure 2. While solder⁴ balls on a FBGA and lead⁵ on a TSOP act as pins, these packages allow the chip to be electrically and mechanically connected with external components.

⁴ Solder: A metal that is capable of both electrical and mechanical bonding as it can melt at low temperature.

⁵ Lead: A wire that emerges from the terminals of an electronic circuit or component to allow connections to a circuit board.

▲ Figure 2. Examples of semiconductor packages (Source: Hanol Publishing)

The Roles of Semiconductor Packaging

Figure 3 shows the four main roles of a semiconductor package: mechanical protection, electrical connections, mechanical connections, and heat dissipation. Of these four roles, the main function of a semiconductor package is to protect the chip and devices from external mechanical and chemical damage by sealing them in package materials such as epoxy mold compound (EMC). Although semiconductor chips are made from hundreds of wafer processes to perform various functions, their base material is silicon. Silicon by itself can break as easily as a piece of glass, and the same applies for structures formed after the numerous wafer processes that are also vulnerable to mechanical and chemical damage. Thus, packaging materials prove to be essential in protecting the chips.

▲ Figure 3. Roles of semiconductor packaging (Source: Hanol Publishing)

Additionally, the semiconductor package is responsible for electrically and mechanically connecting the chip to the system. The package electrically connects the chip to the system to provide power to the chip while also creating a pathway for the input and output of signals. As for the role of mechanical connection, the chip needs to be well connected to the system to ensure they remain physically attached while in use.

At the same time, the packaging needs to quickly dissipate the heat generated by the semiconductor chip and device. When a semiconductor product is operating, a current is flowing. This inevitably creates resistance and then generates heat. As Figure 3 shows, semiconductor packages completely surround chips. If the semiconductor package cannot efficiently dissipate heat, the chip may overheat and cause the internal transistors to heat up too much to operate. Thus, it is essential for the semiconductor package to dissipate heat effectively. As semiconductor products become faster and possess more functions, the cooling function of the package has become increasingly important.

Development Trends in Semiconductor Packaging

Figure 4 outlines the six development trends in semiconductor packaging technology over the years. When considering these trends, we can see how packaging has evolved to fulfill its roles.

First off, materials with good thermal conductivity⁶ and package structures that can effectively dissipate heat have been developed as heat dissipation has become an important factor in the packaging process.

⁶ Thermal conductivity: A measure of the transfer of heat from a high temperature area to a bordering lower temperature area without involving the movement of matter.

The packaging technology which can support high-speed electrical signal transmission is also an important trend, as the packaging can limit the speed of the semiconductor product. For example, if a semiconductor chip or device that can reach a speed of 20 gigabits per second (Gbps) is connected with a semiconductor package that can only support 2 Gbps, the system will perceive the semiconductor to have a speed of 2 Gbps. Regardless of how fast the chip is, the speed of the semiconductor product is greatly affected by the package as the electrical pathway heading to the system is created in the package. This emphasizes how increases in chip speeds need to be followed by similar advancements in semiconductor packages to realize high transmission speeds. This especially applies to technologies in artificial intelligence and 5G wireless communication. In light of this, package technologies such as flip chip⁷ packaging and through-silicon via (TSV)⁸ have been developed to support high-speed electrical signal transmission.

⁷ Flip chip: An interconnection technology which connects chips and substrates electrically with bumps on the substrate flipped over.

⁸ Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

▲ Figure 4. Development trends in semiconductor packaging technology (Source: Hanol Publishing)

Moving on to the next trend, three-dimensional semiconductor stacking technology has become a revolutionary development in the semiconductor packaging field. While only one chip was packaged in the past, there are now technologies that pack multiple chips into one package such as multi-chip package (MCP) and system-in-package (SiP)⁹.

⁹ System-in-package (SiP): A type of packaging that combines multiple devices into a single package to implement a system.

Miniaturization, the process of reducing the size of semiconductor devices, is a trend which has also been applied to packaging technology. As semiconductor products are being implemented in mobile and even wearable products, miniaturization is becoming an important requirement for customers. To meet this demand, many technologies have been developed to reduce packaging size.

Moreover, semiconductor products are increasingly being used in a diverse range of environments. In addition to everyday environments such as the gym, office, or home, they are used in tropical rainforests, polar regions, deep oceans, and even space. As the basic role of the package is to protect the semiconductor chip and device, it is necessary to develop highly reliable packaging technology to enable these semiconductor products to operate normally in these extreme environments.

Lastly, as the semiconductor package is the final product, it is important to develop packaging technologies that have low manufacturing costs and can fulfill desired functions.

Alongside the trends mentioned above that focused on advancing specific roles of packaging technology, another driving force behind the evolution of packaging is the development of the semiconductor industry as a whole. In Figure 5, the red line in the graph represents the change since the 1970s in the feature size of a PCB¹⁰ mounted during the assembly process, and the green line shows the changes in the feature size of a CMOS transistor on the wafer. A decrease in the feature size allows smaller patterns to be drawn on the PCB and the wafer.

¹⁰ PCB (Printed Circuit Board): A semiconductor board that’s made up of electronic circuits and has components soldered on its surface. These boards are found in most electronic devices.

▲ Figure 5. Changes over the years in the feature size of wafers and PCBs (Source: Hanol Publishing)

In the 1970s, the difference of the feature size in PCBs and wafers was relatively small. However, wafers today are being mass-produced and CMOS transistors are being developed to have feature sizes smaller than 10 nanometers (nm), while PCBs still have features sizes in the 100 micrometer (um) range. This gap has widened significantly over the decades.

As the boards are fabricated in the form of panels and there are other factors such as cost-saving tactics, the PCB’s feature size has not changed too much. However, the feature size of CMOS transistors has shrunk dramatically due to advances in photolithography which has widened the gap in sizes with PCBs. The problem is that a semiconductor package must compensate for this difference between a PCB and a wafer, as it is tasked with individualizing the chips cut from the wafer and mounting them on the PCB. This difference in the feature size was not significant in the past, so it was possible to use through-hole technology—where the semiconductor package’s lead is inserted in the socket of the PCB—such as dual in-line package (DIP)¹¹ or zig-zag in-line package (ZIP)¹². However, as the gap grew wider, it became necessary to use technology that attached leads to the surface of the board such as TSOP, which is a type of surface-mount technology (SMT)¹³. Subsequently, packaging technologies such as ball grid array (BGA), flip chip, fan out wafer level chip scale package (WLCSP)¹⁴, and through silicon via (TSV) were developed sequentially to compensate for the widening gap between the wafer and board’s sizes.

¹¹ Dual in-line package (DIP): A package where electrical connection pins are arranged in two parallel rows.

¹² Zig-zag in-line package (ZIP): A package where the pins are arranged in zig-zag form, a replacement for the dual in-line package to increase mounting density.

¹³ Surface Mount Technology (SMT): A package mounting method that fixes a chip to the system board surface via soldering.

¹⁴ Wafer level chip scale package (WLCSP): A variant of flip chip technology which packages integrated circuits at the wafer level. Fan out WLCSP features connections for the package which spread out (“fan out”) beyond the chip’s surface.

Ensuring Effectiveness of Semiconductor Packaging Through Testing

There are two methods to develop a semiconductor package and ensure it works effectively. The first involves using existing packaging technology to create a package suitable for a newly-developed semiconductor chip and evaluating the package. The second method is to develop a new semiconductor packaging technology and then apply it to an existing chip to evaluate the new package’s effectiveness.

In general, it is not common to develop a new chip and apply a new packaging technology at the same time as it is difficult to identify the cause of any problems after the packaging is completed if both the chip and the packaging are untested. Therefore, new packaging technologies are tested with existing mass-produced chips that are known to have few defects in order to verify the packaging technology alone. Once a packaging technology is verified, it can then be applied to the development of new chips and, furthermore, lead to the production of semiconductor products.

Figure 6 shows the packaging development process for a new chip. Normally, the design of the chip and the package is developed together when fabricating a semiconductor product so that their characteristics can be optimized holistically. For this reason, the packaging department looks at whether the chip is packageable before it is designed. During this feasibility study, the package’s design is roughly tested so the electrical, thermal, and structural evaluations can be analyzed to ensure that there would be no problems in the actual mass-production stage. In this context, semiconductor packaging design refers to the wiring design of the substrate or leadframe, which is the medium for the chip to be mounted on the board.

The package department provides feedback to the chip designers on the packages’ feasibility based on the results of the package’s temporary design and analysis. The chip design is only completed when the package feasibility study is finished. This process is followed by wafer fabrication. While the wafers are being fabricated, the package department designs the substrate or leadframe required for package production and proceeds with its production through a company that carries out the back-end process. At the same time, tools for the package process are prepared in advance, and package production begins immediately when the wafers are delivered to the package department after the wafer test.

▲ Figure 6. The development process for semiconductor packaging (Source: Hanol Publishing)

Semiconductor products must be manufactured in packages so that their physical characteristics can be measured and verified. Meanwhile, the design and the processes can be checked with evaluation methods such as a reliability test. If the characteristics and reliability are not satisfied, the cause is investigated and the process is repeated again from the stage where the cause can be resolved. Ultimately, development is only completed after the desired characteristics and reliability standards can be met.

Looking Beyond the Roles of Semiconductor Packaging

As we looked into packaging technology’s role of protecting and connecting various components of a semiconductor, it will also be vital to know which materials and methods are used in this process. The next episode will touch on the differences between conventional and wafer-level packaging while observing how different packaging methods affect the quality and efficiency of this fundamental process.

Read articles from the Front-End Process series

Read articles from the Back-End Process series

The post Semiconductor Back-End Process Episode 2: The Roles, Process, and Evolution of Semiconductor Packaging first appeared on SK hynix Newsroom.

Packaging technology has four main functions. It protects the semiconductor chip from external shock or damage, provides external power and wiring to the chip, and properly distributes heat generated by the chip to ensure stable operation. Additionally, packaging technology acts as a bridge by connecting the gaps existing between semiconductor devices and systems.

Over the past two decades, packaging technology has evolved significantly. These developments include stacking multiple chips onto one package and including chip bumps for interconnection that shortened the signal path to achieve faster operating speeds. Most recently, packaging technology can be considered a system solution by itself as it’s capable of connecting various types of chips into one package and many parts into one module when incorporating a system.

In this EE Times article by Ki-ill Moon, head of Package Technology Development at SK hynix, the author details how SK hynix’s packaging technologies such as Chip-on-Chip (CoC) and Mass Reflow Molded Underfill (MR-MUF) produced vast improvements in speed, cost, and quality.

Today, SK hynix is leading the packaging revolution as it has been mass-producing advanced packaging products based on HBM3 and focusing on investing in production lines and securing resources for the development of future packaging technologies such as heterogenous integration and Fan-out RDL.

As SK hynix always strives to maintain its leadership position in today’s semiconductor memory industry, the company will continue to make innovative efforts to advance its packaging technologies and become a total “solution provider.”

Learn more about the evolution of packaging technology by reading the EE Times article: The Value of Semiconductor Packaging Technology in the Era of Heterogeneous Integration

The post The Value of Semiconductor Packaging Technology in the Era of Heterogeneous Integration first appeared on SK hynix Newsroom.

Image Download

With the opening of the 4th industrial revolution era and the spread of high technologies such as artificial intelligence (AI), 5G, and autonomous driving, the demand for high-performance and ultra-small semiconductors is exploding. Accordingly, “packaging” technology, where semiconductors become solutions to have the best performance and create high added value, is now drawing great attention.

Along with this trend, SK hynix is also focusing on securing future competitiveness by paying attention to the packaging business through active investment and continuous technology development. This time, the newsroom team met with Seung Taek Yang, KI-ILL Moon, Jinwoo Park, and Ho-Young Son – Project Leader (PL) of the SK hynix’s PKG Development Division to hear about the present and the future of SK hynix’s packaging technology including conventional package, Through-Silicon Via (TSV), and Fan-Out Wafer-Level Package (FO-WLP).

Packaging Technology Determines Future Competitiveness as the Key to Increasing the Memory Product Value

After the front-end process where circuits are formed on a wafer, semiconductor chips go through the back-end process consisting of a packaging process and a test. Although a number of fine electric circuits are integrated on a chip, the chip itself cannot perform the role of a semiconductor. The packaging process serves to connect a chip electrically to the outside so that the chip can function properly and protect it from the external environment. Also, another role of packaging is to control heat generation to ensure efficient thermal emission by semiconductors.

With the advancement of semiconductor technology which makes semiconductor products faster and more functional, thermal problems are becoming more and more serious, resulting in the greater importance of the thermal dissipation of semiconductor packages. Also, even if the chip speed is high, as the electrical connection path to the system is made during the packaging process, packaging should also be implemented at a high speed to respond to the faster chip speed. For this reason, cutting-edge packaging technology for the high-density, high-speed, low-power, small-from-factor, and high-reliability semiconductor market is crucial.

Seung Taek Yang PL

Image Download

“Packaging technology is very important for high-performance devices to perform properly. For example, to transmit and receive a large amount of data at once, numerous electric paths connected to the outside should be formed, and what plays this role is the packaging process. Packaging technology stacks multiple chips to implement a capacity of four times, 16 times, or even more compared to the conventional chips, or combines several types of chips to create a system. In other words, depending on the packaging technology, the added value of a product can highly increase. Now, it is an era where chip technology alone cannot preoccupy the future market dominance without advances in packaging technology.”

SK hynix’s Packaging Technology, How Has It Developed?

As mentioned above, semiconductor packaging plays various roles including mechanical protection, electrical connection, mechanical connection, and thermal dissipation. In detail, during the packaging process, semiconductor chips are wrapped with a packaging material such as an Epoxy Molding Compound (EMC)¹ to protect them from external mechanical and chemical impacts. In addition, the packaging process physically or electrically connects the chips to a system to supply power to operate chips, ensures input and output of signals to perform desired functions, and allows dissipation of heat generated when semiconductor products are operated.

The methods of packaging semiconductors can be largely divided into two types. One is the conventional package, which is a traditional method of applying a packaging process to individual chips separated from wafers. The other is the Wafer-Level Package (WLP), where part or all of the process is carried out at the wafer stage and later cut into single pieces.

Image Download

In the packaging field as well, SK hynix has continuously developed and created innovative products from the past to the present. The early packaging technology used in 1986, when DRAM development and production began in earnest, was the lead frame² method that connects chips and pads by using gold wires. Soon after, however, the lead frame structure faced its limit, with the improvement in the device performance. Accordingly, other structures such as the Fine-Pitch Ball Grid Array (FBGA)³ based on a substrate are applied. This type of package is a conventional package, which is mainly applied to high-density NAND or mobile DRAM products since it can stack many chips in a package.

Since then, to meet the high-performance specifications required for memory products, the existing method of the conventional package has been developed and the new method of WLP has begun to be introduced, resulting in two paths of the development of the packaging technology. In particular, WLP technology is suitable for realizing high-performance products. Since packaging in the same size as the chip is possible when using this technology, it can minimize the size of finished semiconductor products. Also, saving cost is another advantage of this technology as it does not require materials such as substrates or wires.

From 2007, SK hynix has introduced the flip chip⁴ process, a technology that combines conventional packaging and WLP in graphics DRAM that requires high performance, while applying the Redistribution Layer (RDL)⁵ process to the main memory. From 2007 to 2010, SK hynix revealed a series of memory modules to which the Wafer-Level Chip Scale Package (WLCSP)⁶ was applied for the first time in the world. Based on this technology, the company applied the 3-Dimensional Stack (3DS)⁷ and introduced a 128 GB DRAM module.

More recently, the WLP process is mainly used for products such as High Bandwidth Memory (HBM), which needs to satisfy the needs for high density and high performance, and Computing DRAM, which requires much more capacity than existing products.

In 2013, SK hynix succeeded in developing and mass-producing HBM with TSV structure for the first time in the world and mass-produced 3DS products developed for High-Density products. In 2019, the company developed HBM2E and succeeded in mass-producing it just in 10 months, preoccupying a clear advantage in the HBM market and maintaining it until now.

Image Download

Next-Generation Packaging Technology as a Growth Source of SK hynix

With the increase in the demand for high-performance and ultra-small semiconductors, packaging technology is emerging as a core technology for the next-generation semiconductors to enhance semiconductor performance and production efficiency. Accordingly, SK hynix is actively developing innovative technologies to raise the value of memory solutions by strengthening the packaging competitiveness in the fields of the conventional package, TSV, and FO-WLP.

▶ “Conventional Package” through a Total Solution of Materials, Processes, and Equipment

For a single package to implement High Density, the key is to stack chips as thin as possible, which requires high-level element technologies. In this regard, KI ILL Moon PL explained the SK hynix’s technology level by presenting an index of “chip stack count”.

KI ILL Moon PL

Image Download

“SK hynix’s packaging technology is the highest level in the industry. In the case of mobile DRAM, 16 GB is achieved by integrating 16 units of 8 Gb memory in one package. In the case of NAND, a product in which 16 layers are stacked in a package is mass-produced. In addition, SK hynix is in the process of securing element technology to apply 32-layer stacking technology to mass-produced products for the first time in the industry.”

What is the competitiveness unique to SK hynix, especially in the conventional package stage to survive in the increasingly fierce competition for miniaturization and stacking? Currently, SK hynix is preparing various solutions to maximize the performance required for each characteristic of memory products.

In computing and graphics memory, the power control function is crucial as well as high speed. To achieve this, SK hynix is preparing thermal dissipation solutions for easier power control. In terms of materials and structures, the company is developing various solutions including thermal dissipation EMC and Exposed Mold Package. Also, in the case of mobile memory where the speed determines its competitiveness, wire bonding technology is being developed to reduce signal delay or capacity.

In NAND, the complex solution of the combination of controller and DRAM determines the competitiveness. For this reason, SK hynix is developing element technologies in advance so that they can be used as needed to ensure a timely supply of various solutions to customers.

As the performance of electronic products evolves, the required level for semiconductors continues to increase as well. How can SK hynix overcome the limitations in the future? Moon PL said, “Every moment, we have been facing a limit and even now, we are facing one. However, we always have been overcoming the limit, like we are now.”

For instance, just a few years ago, it was considered impossible to reduce the chip thickness below 50 ㎛ to stack eight DRAMs. Now, however, it has become a very common technology. Moon PL said, “The reason we could overcome the limit at that time was the development of the equipment, processes, and materials that could handle thin dies. We will continue to take the lead in overcoming the limits in the future through various efforts such as boundless cooperation encompassing different functions of materials, processes, and equipment in the packaging field and seeking for a total solution.”

▶ “TSV” for Realizing High-Performance and High-Density Memory

To become a winner in the ultra-speed memory HBM market, a technology gap with competitors should be widened, going beyond the level of customer demand. To achieve this, the PKG Development Division developed an exclusive, specialized technology called Mass Reflow Molded Underfill (MR-MUF)⁸ for the first time in the world and applied it to HBM products. Based on this technology, the thermal dissipation performance has been improved by more than 10℃ compared to competitors.

Image Download

Meanwhile, TSV technology was the key to the innovative enhancement in the processing speed of HBM2E, “the world’s fastest DRAM”. SK hynix has implemented 16 GB, which is more than double compared to the previous generation by connecting eight 16 Gb DRAM chips vertically with the TSV technology. TSV is one of the WLP technologies that SK hynix is currently focusing on, and SK hynix has the highest level of TSV competitiveness in the industry.

Jinwoo Park PL

Image Download

“SK hynix has secured element technologies essential for stably handling thin wafers and stacking thin chips. We have developed the Advanced Mass Reflow method, which can stack 30㎛-thick chips in multiple layers as of today. Another competitiveness of SK hynix is the organizational power to ‘realize what we need to do’ rather than ‘realize what we can do’, based on the experience of succeeding in the HBM2E development. Our differentiated competitiveness is the process of collaborating between members and seeking a solution together even in difficult situations.”

In addition to the HBM2E, 3DS products are also one of the examples of innovation in TSV technology. Previously, the Mass Reflow (MR)⁹ process commonly used in the flip chip method had been converted to the Thermal Compression (TC)¹⁰ process for multi-layer stacking and miniaturization, but it has reached the limit of productivity. To overcome this, SK hynix applied the MR method to 3DS for the first time in the world, enabling stable production and quality control. This product is expected to be even more highly favored in the near future, since the DDR5 high-density market will be completely converted to 3DS.

SK hynix’s goal this year is to increase the TSV product line and secure profitability. To achieve this goal, company-wide efforts are being made.

Park PL said, “The core of the TSV technology is to implement stacking in a stable structure, quickly and cost-effectively. The TSV technology is applied only to HBM and 3DS products currently, but this can be extended and applied to mobile and NAND products, when high processing speed is needed. In preparation for this, we are working hard in collaboration with many other departments to proactively secure cost competitiveness.

▶ “FO-WLP”, a Packaging Technology of the Next Generation

In addition to the flagship packaging technology, SK hynix is focusing on the “Fan-Out Wafer-Level Package (FO-WLP)” as a growth source and a technology to contribute to profit generation in the future.

Wafer-Level Chip Scale Package (WLCSP) can be divided into Fan-In Wafer-Level Package (FI-WLP) and Fan-Out Wafer-Level Package (FO-WLP). Both technologies adopt a method of packaging by attaching solder balls (I/O terminals) directly onto the chip without a medium such as a substrate. As the length of wiring is reduced, the electrical characteristics are improved, and more chips can be stacked by reducing the package thickness.

Here, the “fan” refers to the chip size. When the chip size is the same as the package size and the solder balls for packages are implemented within the chip size, it is called “fan-in”. When the package size is larger than the chip size and the solder balls are implemented outside the chip as well, it is called “fan-out”.

Image Download

In the case of FI-WLP, where the chip size is just same as the package size, it has a disadvantage of having to establish a new package infrastructure when a new chip is developed, since a new chip requires a different package size even though it has the same function as the previous one. In addition, if the size of the package solder ball arrangement is larger than the chip size, the package cannot be made. It is also inefficient in that defective chips should be packaged as well, since the wafer is cut after the packaging process is completed. On the contrary, in the case of FO-WLP, there is no need to package defective chips because chips are cut first before the process. Since the package size can be adjusted, it is possible to use the existing package test infrastructure and it is easy to implement the desired package solder ball arrangement. Especially, it is advantageous in that different chips can be mounted in a single package as horizontal connection with heterogeneous chips is possible.

Ho-Young Son PL

Image Download

“FO-WLP is mainly used for packaging at least two heterogeneous devices such as packaging different System on a Chip (SoC) dies or packaging an SoC and a memory chip together. It is considered a next-generation packaging technology that will satisfy the demand for high-performance products. For this reason, many foundry companies are jumping into the back-end process technology development and expanding the market based on high technology and solid business models. SK hynix is also strengthening its investments in infrastructure related to FO-WLP technology, aiming for the company’s mid to long-term growth. Also, SK hynix is steadily preparing for the application of the FO-WLP technology for each memory application, as well as developing element technologies step by step to implement products.”

Currently, SK hynix is priorly reviewing adopting the FO-WLP to memory products. It is expected that it will significantly improve the package size and device characteristics by eliminating the need to use substrate while stacking multiple, identical chips. This will be also useful to implement a package structure that dramatically improves the performance limit of the current DRAM. Ultimately, it is expected to accelerate the development of direct packaging technology for heterogeneous devices such as memory and SoC and facilitate active participation in the semiconductor ecosystem environment.

Meanwhile, Son PL emphasized the necessity of understanding the memory system better than anything else. Based on the understanding, especially on the limitations of the current memory devices, it is important to find a solution through close cooperation between related departments to overcome such limitations, Son PL said.

In addition, he showed the determination to lead the semiconductor market in the new path based on the next-generation packaging technology.

He said, “HBM products were developed by SK hynix for the first time in the world eight years ago, and have been advanced through many trials and errors. Only recently, they have become technologically competitive and started to contribute to financial achievements. Looking back to this, you can see that it takes a long time for new technology to be adopted in the market and contribute to generating profits. This also means that if we do not prepare for the future from this moment, we will not be able to survive the rapidly changing semiconductor competition.”

Lastly, he expressed his confidence in SK hynix’s future, by saying, “We believe that we will be able to lead the market with competitive technologies if we continue to carefully prepare new technologies step by step without limiting ourselves. A number of members from various related departments, not only the PKG Development Division, are working hard together, so you can look forward to the future of SK hynix.”

Image Download

Based on the technological prowess and the experience of success that have been solidly accumulated over time, the PKG Development Division overcomes limitations and is moving toward the next step. The four PKG Development leaders, who undertake a key mission to strengthen SK hynix’s future competitiveness, delivered a message of their ambition to stakeholders.

“In the current environment, we cannot survive with the device development alone. Our way forward is to develop products that meet customers’ need in a timely manner through collaboration between the device and packaging fields. Also, even with the same product, we will need to constantly study strategies for securing differentiated advantages compared to our competitors. In that sense, we expect that packaging will play a key role. To lead the packaging field, numerous members of SK hynix are working hard even at this moment in various areas from technology development to cost reduction and customer response. You can look forward to the SK hynix’s future!”

Articles related to packaging technology

SK hynix CEO Seok-Hee Lee Talks about the Future of Semiconductor Memory and SK hynix’s Management Strategy
https://news.skhynix.com/sk-hynix-ceo-seok-hee-lee-talks-about-the-future-of-memory-semiconductor-and-sk-hynixs-management-strategy/

[Top TL] P&T Enhances the Value of Memory Solutions: Sang Hoo Hong, Head of P&T
https://news.skhynix.com/top-tl-pt-enhances-the-value-of-memory-solutions-sang-hoo-hong-head-of-pt/

Behind-the-scenes Story of “HBM2E”, the Fastest DRAM in History
https://news.skhynix.com/behind-the-scenes-story-ofhbm2e-the-fastest-dram-in-history/

¹Epoxy molding compound (EMC): Thermosetting plastic with excellent mechanical and electrical insulation and temperature resistance characteristics, as a resin with relatively low molecular weight, capable of three-dimensional curing in the presence of a hardener or catalyst
²Lead frame: A lead refers to a line that comes out of an electronic circuit or a terminal of an electric component and is used to connect an electronic component to a circuit board. Lead frame refers to a shaped metal plate of an inner/outer lead used when assembling a semiconductor chip; as a thin metal plate that attaches chips cut from a wafer, leads, etc. to be used in a package are formed.
³Fine-Pitch Ball Grid Array (FBGA): As a substrate type package, a package in which a pin that serves as an electrical and mechanical connection between the package and PCB is formed of a ball-shaped solder ball is called a Ball Grid Array (BGA). Among the BGA, a package with solder balls in a small distance is called FBGA, by attaching “fine” to BGA.
⁴Flip Chip: An interconnection technology where bumps are formed on a chip’s bond pad, flipped over, and bonded to a board such as a substrate; compared to wire bonding, which is a technology that electrically connects the top of a chip and a substrate or lead frame with wires by using heat and ultrasonic waves, the mounting area and height can be reduced and the electrical characteristics can be improved.
⁵Redistribution layer (RDL): A generic term for technologies that form a metal wiring layer using the wafer-level package process method and change the position of the existing chip pad to the desired position
⁶Wafer-Level Chip Scale Package (WLCSP): Unlike conventional packaging technology, where packaging is done by cutting a wafer into chip units after the fab process is completed at the wafer level, wafer-level packaging is done as a wafer-level process rather than a chip-level process and produces a single piece of the product.
⁷3D-Dimensional Stack (3DS): In a broad sense, it refers to a package where at least two IC chips are vertically stacked. More specifically, however, it refers to a package where the inside of stacked DRAM chips is electrically connected by using TSV. 3DS memory is made into a BGA package, which is then mounted on a PCB to make a product in the form of a memory module.
⁸Mass Reflow Molded Underfill (MR-MUF): A molding compounding process that secures gap filling in the flip chip process, while performing molding at the same time
⁹Mass reflow (MR): A process where multiple devices are aligned and placed on a substrate and heated in an oven, etc., to melt solders to bond them altogether; since it is carried out all at once, the word “mass” is used in this term.
¹⁰Thermal compression (TC): A method of bonding by applying heat and pressure to the junction where flip chip bonding is performed

The post Packaging Technology, a Key to Next-Generation Semiconductor Competitiveness, How Far Has SK hynix Come? first appeared on SK hynix Newsroom.