This final episode in the Tech Pathfinder series will introduce SK hynix’s advanced 4D NAND technologies. These include its 4D^1.0 technologies, which specialize in stacking and performance improvement such as the Cost-Effective 3-Plug formation, Sideway Source, All Peri.¹ Under Cell (PUC), and Advanced Charge Trap Flash (CTF). It will also cover the 4D^2.0 NAND technologies which overcome the limitations of stacking, such as Multi-Site Cell (MSC).

¹Peripheral circuit (peri.): A circuit that controls the cell.

The Basics of NAND Flash Memory

For a better understanding of 4D NAND technology, it is prudent to review NAND’s basic concepts and related terminology.

Figure 1. An overview of different types of NAND flash memory

A cell is the smallest unit in which information is stored. In NAND flash memory, the cells consist of a control gate and a floating gate. When voltage is applied to the control gate, electrons traveling through the pathway are stored in the floating gate. NAND flash stores data by categorizing cells as either 0 or 1 using electrons stored on the floating gate. This state is characterized by the number of electrons in a cell. For example, a cell with few electrons is read as 0, while a cell with a high number of electrons is interpreted as 1.

NAND flash memory is categorized into different types depending on how much information (bits) is stored in a single cell. These include single-level cell (SLC, 1 bit), multi-level cell (MLC, 2 bits), triple-level cell (TLC, 3 bits), quad-level cell (QLC, 4 bits), and penta-level cell (PLC, 5 bits). As for the units used to measure NAND flash memory capacity, these include references to giga (a billion) and tera (a trillion). In other words, a TLC NAND flash product with a capacity of 1 Tb has about 330 billion cells that store 3 bits each.

4D^1.0 Technology: Reducing Chip Size Through Cell Stacking

There are four main 4D^1.0 NAND technologies SK hynix has employed to develop high-capacity NAND flash solutions.

Figure 2. An overview of the Cost-Effective 3-Plug formation and Sideway Source

Cost-Effective 3-Plug Formation

One of the key goals of developing semiconductor technology is improving cost efficiency. This is achieved by stacking more cells to reduce the chip size and producing as many chips as possible on a single wafer. Stacking substrates layer-by-layer and repeating the cell formation process for each layer would be inefficient and increase manufacturing costs. Therefore, multiple layers of substrate are first stacked, then vertical holes called plugs are drilled through the layers before cells are formed next to the holes.

As the number of layers increases, the more challenging it becomes to form plugs to the bottom layer as existing etching equipment can only etch around 100 layers at a time. Therefore, to develop a NAND flash product with more than 300 layers, it is necessary to stack 100 layers and perform the plug etching process three times. This is where SK hynix’s Cost-Effective 3-Plug formation is used as all the processes, including cell formation, can be performed simultaneously on all layers.

With this, SK hynix was able to conduct a single process to simultaneously fabricate the key structures—word lines² and word line staircases³—that apply voltage and the passageways for electrons. This enabled the company to unveil a 321-layer 4D NAND of the highest density in August 2023 while minimizing costs.

²Word lines: The structure that binds the control gate of each layer of NAND cells.
³Word line staircases: A staircase-like structure for exposing the word line of each layer to the top surface.

Sideway Source

Semiconductor plugs provide a pathway for electrons to travel. Inside a plug, this pathway is covered by CTF film⁴. Therefore, the CTF film needs to be removed at the connection point where the plug and the bottom of the NAND flash layer meet to connect two pathways. Sideway source connects the plug to the bottom of the NAND flash layer (channel and source line⁵). Previously, etching gas was injected from the top of the plug to vertically remove the CTF film at the bottom of the plug. However, when stacking two or more plugs, the centers of the plugs were not aligned. This prevented the etching gas from reaching the bottom, damaging the CTF film on the side of the plug that serves as a cell.

⁴CTF film: A composite of oxide and nitride films that replaces the floating gate.
⁵Source line: Located at the bottom of a NAND layer, the source line is part of a channel inside the plug. Electrons from the source line travel up the channel to the top of the NAND layer and are stored in their respective floating gates.

SK hynix solved this issue by replacing the vertical connection with a horizontal one. The etching gas is injected into a separate pathway to reach the bottom of the NAND layer and remove the CTF film on both sides of the plug.

With Sideway Source technology, the etching gas is not directly injected into the plug. Therefore, even if the plugs are misaligned, the interior remains undamaged. As a result, SK hynix has significantly reduced its defect rate, increased productivity, and addressed the problem of increased costs associated with multiple stacking.

Since SK hynix introduced the industry’s first 4D NAND in 2018, it has enhanced its expertise to produce precise horizontal pathway connections which leave no voids at the bottom of the NAND layer. Based on this advancement, the company improved production efficiency by 34% for its 238-layer NAND flash memory compared to the 176-layer product and further solidified its market leadership with its 321-layer NAND.

Figure 3. An overview of All Peri. Under Cell (PUC)

All Peri. Under Cell (PUC)

PUC reduces the chip size and increases the number of stacks by placing the peripheral circuit (peri.) under the cell. SK hynix used PUC to develop a new NAND flash structure, the world’s first 4D NAND, and then began product development. The company has further developed upon PUC with its All PUC technology, which miniaturizes the peri. so it becomes the same size as the cell or smaller to accommodate the reduced cell size. To advance the technology, SK hynix is further miniaturizing the peri. by reducing the size and number of transistors and fully placing the peri. in the empty space under the cell.

In particular, this technology was used for the first time to great effect in SK hynix’s 238-layer 512 Gb TLC NAND. For this solution, the company reduced the size of the chip and peri. by more than 30% compared to the previous generation, thus improving production efficiency and cost competitiveness. SK hynix will continue to enhance its expertise and perfect the technology so it can be applied to future products that require a smaller peri. and chips.

Figure 4. An overview of Advanced Charge Trap Flash (CTF)

Advanced Charge Trap Flash (CTF)

Advanced CTF minimizes data degradation by retaining more electrons than conventional CTF. In CTF, electrons are stored in nonconductors rather than in conductors such as a floating gate. CTF was therefore developed in part to address inter-cell interference⁶ in conductors by changing the electron storage space to nonconductors. However, electrons often escape from nonconductors as they are stored in the voids of the CTF material (nitrogen-silicon compound) which has unstable areas. When electrons are stored in these unstable areas, the bonds quickly break and the electrons are ejected, resulting in data loss.

⁶Inter-cell interference: Electrons in a cell are affected by electrons in adjacent cells due to device miniaturization, resulting in data corruption.

For its Advanced CTF, SK hynix fills the unstable areas with hydrogen to prevent electrons from entering, and increases the number of binding agents to store more electrons. Furthermore,  Advanced CTF also increases the number of electrons stored in CTF by minimizing the risk of escaped electrons. This improves the ability to determine electron counts, reduces read errors, and significantly shortens latency.

Some types of NAND flash have difficulties distinguishing data when there are a low number of electrons, resulting in errors. For example, if SLC flash memory distinguishes data using ten electrons, data with one to five electrons is 0, and data with six to ten electrons is 1. However, if five electrons escape, the data previously processed as 1 is distorted and an error occurs. This problem worsens as a cell is segmented to the MLC level and higher.

TLC differentiates between eight states from 000 to 111. If there are 10 electrons to distinguish, each state is assigned either one or two electrons. This is a significant difference from SLC, which allocates five electrons per state. Consequently, even if only a few electrons escape, it can lead to data corruption.

In contrast, consider a situation in which Advanced CTF was used to distinguish data with 100 electrons. If the number of electrons is between 0 and 50, the data is read as 0, while if it is between 51 and 100, it is 1. Even if some electrons escape, the large number of electrons overall greatly reduces the chance of misreading the data. Since there are few errors, the latency is shortened, and the read speed increases.

SK hynix first applied Advanced CTF to its 176-layer NAND solution, resulting in a 25% improvement in the ability to determine electron counts. As Advanced CTF-based memory solutions offer lower latency, they are particularly suited for the gaming and automotive markets which require rapid data processing.

4D^2.0 Technology: Increasing Horizontal Cell Density & Stacking for Enhanced Performance & Density

When developing semiconductor memory, manufacturing costs continue to rise with each additional layer. Taking into account the additional cost of increasing the number of bits beyond the TLC level, there comes a point where it is no longer possible to reduce costs. In response, SK hynix is developing 4D^2.0 technology which increases the number of layers and horizontal density of cells to improve storage capacity relative to cost. Multi-Site Cell (MSC) is a 4D^2.0 technology that structurally improves the horizontal density, thereby significantly increasing the number of bits.

Figure 5. An overview of Multi-Site Cell (MSC)

Multi-Site Cell (MSC)

There are two primary methods for horizontally expanding cell density. The first is multi-level cell (MLC) technology, which subdivides electron counts to accommodate more data (bits) in a single cell. This is the case with NAND flash types ranging from SLC to QLC. The second is MSC technology, which structurally increases the sites where electrons are stored in a cell, enabling it to hold more data (bits).

MLC technology has been commercialized in 4-bit QLC products, but it is challenging to maintain performance and reliability in 5-bit PLC and beyond. This is due to the previously mentioned limitations in determining electron counts.

For example, if you build a 6-bit hexa-level cell (HLC) with MLC, you need to store data in 64 different states ranging from 000000 to 111111. This is prone to errors and time-consuming because there are not enough electrons to distinguish each state. Compared to the 4-bit QLC, the ability to determine the number of electrons is four times poorer.

On the other hand, when developing an HLC with MSC, eight states from 000 to 111 are created in two spaces and multiplied to realize 64 states to store data. Compared to the 4-bit QLC, the ability to distinguish electron counts doubles. In other words, it has the capacity of an HLC but the speed of a TLC. SK hynix has confirmed a 20-fold improvement⁷ in read and write speeds when utilizing MSC. Due to MSC’s high capacity, rapid speed, and reliability, SK hynix’s NAND flash is the leading solution for future multimodal AI⁸.

⁷Comparison between a 5-bit regular cell and a 2.5-bit × 2.5-bit MSC
⁸Multimodal AI: AI that can simultaneously process text, speech, images, etc.

Solving Industry Problems With An Eye on the Future

In this final Tech Pathfinder episode, SK hynix’s 4D NAND technologies were shown to solve the industry issues of today and tomorrow. The company’s 4D^1.0 technologies improve the cost-effectiveness and performance of its NAND flash, while its 4D^2.0 technologies will overcome stacking limitations set to arise in the future.

<Other articles from this series>

[Tech Pathfinder] HKMG Opens the Door to Leading Mobile DRAM LPDDR5X & LPDDR5T

[Tech Pathfinder] Small Size, Big Impact: Unveiling the Latest Advances in Semiconductor Packaging and Miniaturization

The post [Tech Pathfinder] How SK hynix’s Advanced 4D NAND Technologies Are Overcoming Stacking Limitations first appeared on SK hynix Newsroom.

The industry’s solution to these limitations was found in a back-end packaging technology which offered enhancements in performance, efficiency, and capacity. Referred to as advanced packaging technology, it revolutionized heterogeneous integration that brings together different types of chips, such as DRAM and NAND, and increased bandwidth by stacking DRAMs vertically.

Heterogeneous Integration Spurred on by Advanced Packaging Technologies

While SK hynix has continued to introduce its next-generation semiconductors at several domestic and global conferences, the company’s key focus has been on heterogeneous integration, which involves the integration of semiconductor memory and logic semiconductors.

This is the idea of bringing together different chips in close proximity with each other to minimize the traveling paths for data used in computations, resulting in a single package with advanced performance and efficiency. Known as a system-in-package (SiP)¹, it fundamentally needs miniaturization as well as advanced packaging technology.

¹ System-in-package (SiP): Multiple integrated circuits bundled into a single package, capable of performing all or most of the functions of an electronic system.

SK hynix considers the next 40 years as the era of heterogeneous integration, which is why it continues to focus on developing advanced packaging technologies to introduce new products with high performance and capacity. Chiplet, multi-chip packaging (MCP), vertical wire fan-out (VFO), and advanced mass reflow-molded underfill (MR-MUF) are some of the main technologies for heterogeneous integration. In this second episode in our Tech Pathfinder series, it will explain in detail these technologies’ concepts, processes, benefits, and applications.

Chiplets: Breaking Down Chips to Incorporate Their Functions in One Package

Semiconductors are made up of components with different functions. A CPU alone is a combination of computation, storage, power, and data input/output (I/O) functions. Likewise, a semiconductor is the end result of fabricating various components at once and packaging them all together.

While it was common to make semiconductors this way in the past, problems started to arise with the continuation of miniaturization and the need to consistently improve performance. If each chip with a distinct function is compared to a candy and the semiconductor is a candy gift basket, the volume of the gift basket will keep increasing as more candies are added. To accommodate this growing number of candies, the internal arrangements of the gift box will also become more complex. If a candy breaks, the inside of the gift basket would be filled with crumbs and the whole gift basket would lose value. The same applies to a semiconductor that features a bad device.

As the semiconductor industry started to think about solutions to this problem, a question arose: what if the devices were made and packaged separately? Thus, the solution was to fabricate each area of the semiconductor separately. This is known as chiplet technology which divides a monolithic chip by function and puts it back together again. In other words, chips that are fabricated for computation, storage, power, data entry, and other functions are made and packaged separately. Lastly, they are combined at the packaging stage of the back-end process. The separated chip pieces are called chiplets, and they can be freely arranged and assembled in any way much like Lego blocks.

Chiplets offer a range of advantages. As the chips are broken down into smaller pieces, the entire chip does not need to be discarded due to a bad device in a particular area. Just the individual chiplets can be replaced with a new chiplet that has already been fabricated. In addition, since chiplets are made from multiple small dies², more net dies can be produced on a wafer which results in higher yields. Lastly, different processes can be applied to chiplets. For example, core chiplets can be made with a 10 nanometer (nm) process, while other chiplets can be made with a 20nm process. Thus, the development efficiency and costs can be controlled by focusing resources only to chiplets that require high performance. Returning to the candy analogy, simple candies can be made on a relatively inexpensive machine but those which require more complex processes such as adding chocolate must be made on a more expensive machine. This feature of chiplets has made it possible to fabricate semiconductors at a lower cost and with higher efficiency.

² Die: Each chip is referred to as a die before it is cut from the wafer.

▲ Figure 1. The process of packaging chiplets and its advantages

As shown in Figure 1, the basic concept of a chiplet is to combine devices a-1 and a-2 that possess different functions. Chips that are separated by function are interconnected on a substrate to become 2D, 2.5D, or 3D structures. Different chips are stacked horizontally in a 2D structure, while a 3D structure features vertically stacked chips. Meanwhile, a 2.5D structure includes an RDL interposer³ inserted between a 2D chiplets and a substrate. This silicon circuit board is thinner than the substrate and has data I/O terminals with a higher density. This means that the data paths are densely packed. An RDL interposer can be likened to a bike path next to a sidewalk that allows cyclists to travel faster. Since high-performance circuits like this can achieve faster data speeds, they are referred to as 2.5D despite technically being 2D.

Meanwhile, SK hynix is developing chiplet technology to be applied to its CXL⁴ memory controllers. The controller chiplets are each placed at the minimum distance of 2.5D from targets they correspond with, and this structure is expected to improve communication speeds and memory scalability. Accordingly, CXL memory with chiplets is set to be a significant solution in the era of big data and AI, and will act as a pillar in future high-performance computing systems.

³ Redistribution layer (RDL) interposer: The construction of a new circuit in the middle to electrically connect a smaller semiconductor circuit with a larger substrate circuit.

⁴ Compute Express Link (CXL): A PCIe-based, next-generation interconnect protocol for efficiently building high-performance computing systems. Enables more efficient integrated utilization of various solutions such as memory, GPUs, AI accelerators, etc.

Multi-Chip Package (MCP): Bringing Memory Chips Together for High-Performance Products

Multi-chip package (MCP) is a technology that vertically stacks multiple memory chips into one package. While MCP may sound similar to chiplets, there are fundamental differences between the two. For one, MCP specializes in memory products like NAND and DRAM, and the combination of these two products can make an MCP. For one, MCP specializes in stacking memory products like NAND and DRAM, stacks NAND and DRAM, which are thin chips with completely different properties. In the past, a package stacked with multiple homogeneous chips was considered to be an MCP, but it is more common these days for an MCP to combine multiple heterogeneous chips.

Efficiency enhancement and mobile optimization are the main reasons for stacking multiple chips. This is because chip stacking minimizes both power consumption and space taken by chips while maintaining a large capacity. This leads to the benefits of using MCPs. Firstly, even if numerous chips are in an MCP, the package will remain thin as MCPs are manufactured to a thickness standard of 1.4 mm or less as defined by microelectronics standards body JEDEC in response to customer and market trends. Hence, the thin and small chips in an MCP take up a minimal amount of space. Additionally, MCPs also simplify the process of attaching to a device. Compared to mounting NANDs and DRAMs separately on a device’s main printed circuit board (PCB), MCPs simplify the manufacturing process. Lastly, power efficiency is also improved by running multiple chips at once. For these reasons, MCPs are often used in mobile devices where smaller chips are preferred.

▲ Figure 2. The different methods of fabricating MCPs and their advantages

MCPs can consist of many different combinations of chips. For example, NANDs and DRAMs can be separately stacked on a substrate through planar vertical stacking or NANDs can be stacked on top of DRAMs through mixed vertical stacking. When MCPs are stacked like this, each chip is attached with a die attach film (DAF)⁵ and connected to the substrate with wires made of substances like gold, copper, and aluminum. The chips are then wrapped in a protective material that is made from epoxy mold compound (EMC)⁶ to complete the packaging process.

⁵ Die attach film (DAF): A thin adhesive film that protects the chip and bonds the semiconductor to the substrate.

⁶ Epoxy molding compound (EMC): An epoxy resin-based heat dissipation material capable of sealing the chip to protect it from external impacts like heat, moisture, and shock.

SK hynix has been fabricating MCPs for more than two decades. A key breakthrough was made in 2007 when the company introduced the world’s first 24-layer NAND MCP. Since then, it has been offering competitive MCP products through its sophisticated processes that are capable of controlling and stacking chips of 50 micrometers (μm) or less. SK hynix plans to continue developing these highly integrated products to increase profitability and meet the rising demand from global mobile markets.

Vertical Wire Fan-Out (VFO): Combining Fan-Out WLP With DRAM Stacking

Vertical wire fan-out (VFO) is based on the principle that it is quicker and shorter to travel along a straight line than a curved one. This applies to the wires that connect chips and circuit boards. Consequently, VFO is a technology that minimizes space and reduces power consumption by connecting wires vertically instead of curving them. It has also revolutionized the sizeable fan-out wafer-level package (WLP), a packaging technology which connects I/O terminals with wires from the outside of the chip.

The advantages of using fan-out WLP include the capability to develop thinner packages due to the lack of a substrate. It also offers improved electrical characteristics and higher thermal efficiency thanks to the reduced length of wiring between the chips and the main board. Moreover, the technology can be applied to high-performance products as it provides more data I/O points. However, despite its advanced characteristics, the use of fan-out WLP technology in semiconductor memories has been limited. The structure resulting from stacking chips and connecting them to a substrate with curved wires on either side did not turn out to be a good method for applying fan-out WLP to semiconductor memories.

The world’s first VFO developed by SK hynix overcomes this limitation. By utilizing vertical wires to connect stacked DRAMs, the company was able to realize the optimal fan-out WLP. These vertical wires changed the path that electrical signals travel along from long and curved to short and straight to increase the power efficiency. This can be compared to driving through a tunnel instead of driving around a mountain to get to the destination with less time and effort. These benefits were highlighted during IEEE Electron Devices Technology and Manufacturing (EDTM) 2023, later being mentioned as a memory technology that goes hand-in-hand with today’s mobile device trends.

▲Figure 3. The VFP process and its various benefits

Recently, SK hynix completed the development of VFO technology and started its verification process, and this led to significant results when applied to LPDDR products. Compared to products that use conventional wiring, the wire length was reduced 4.6 times and power efficiency improved by 4.9%. While heat dissipation also increased by 1.4%, the most noticeable advancement was the 27% reduction in package thickness.

In recent years, the industry has accelerated the adoption of fan-out WLP to keep pace with the high specifications of smartphones and to secure battery capacity in such devices by reducing the size of components. VFO will help SK hynix develop more mobile-optimized memory products to meet customer demands and contribute significantly to the global market.

Advanced Mass Reflow Molded Underfill (MR-MUF): Connecting Vertically Stacked Chips With Ease

It is important to understand the concept behind mass reflow-molded underfill (MR-MUF) before talking about advanced MR-MUF. Firstly, MR-MUF is a technology which is used to stack multiple chips and package them. It is used commonly in High Bandwidth Memory (HBM), which increases the number of data paths, or bandwidth, by stacking multiple DRAM chips with TSV⁷. The thousands of data paths that vertically run through the stacked chips are connected without wiring and are later wrapped with MR-MUF.

⁷ Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice. SK hynix utilized TSV technology to develop HBM3 with data processing speeds up to 819 GB/s (819 gigabytes per second)

▲ Figure 4. Characteristics of advanced MR-MUF and its advantages

Ultimately, MR-MUF is the technology that can efficiently connect vertically stacked chips. This allows multiple chips to be packaged at once, making it an innovative technology for semiconductor processes that increases productivity and improves product reliability.

To better understand the process of MR-MUF, it will be helpful to separately look at the roles of mass reflow (MR) and molded underfill (MUF). When MR connects vertically stacked chips and circuits, a micro bump that acts as a bridge is placed underneath each chip’s connection passage. As the lead material in the bump melts, the top and bottom pathways of the chip are connected. Melting all of these bumps at once to connect the chip is called reflow. It adds the prefix “mass” to indicate that a large number of bumps are melted. Meanwhile, MUF is a technology used to protect chips by applying protective materials to external areas including between and around chips. The process of filling between chips with the protective material is called underfill and the method of wrapping the chips is known as molding⁸, and they are performed simultaneously.

⁸ Molding: The process of sealing wire-bonded or flip chip bonded semiconductor products with an epoxy molding compound (EMC).

So, why is it called “advanced” MR-MUF? It is because the technology improves existing shortcomings of MR-MUF. As reflow runs at high temperatures during MR-MUF, this causes warpage on the chip, making it challenging to apply an MR-MUF process in the past. Likewise, SK hynix continued using MR-MUF because of its advantages, but a problem arose when developing its 12-layer HBM3. Moreover, due to the chip having to be 40% thinner for 12-layer HBM3, it was necessary to develop new technologies to overcome warpage. In response, SK hynix introduced the industry’s first chip control technology and improved heat dissipation with new protective materials. The result of these two technologies is the advanced MR-MUF.

Chip control technology is implemented by applying a momentary burst of high heat to each chip as it is stacked. This causes the bump under the top chip to fuse to a thin pad on top of the bottom chip. The pad holds the chip together and prevents it from warpage. This process is repeated for each stack of chips. At the end of the process, the MR-MUF is finalized and the chip is packaged in a new protective material that provides better heat dissipation.

The reason SK hynix is continuing to utilize MR-MUF and even develop advanced related processes is because of its reliability and efficiency. MR-MUF follows the same principles of an oven that evenly distributes heat to food. Likewise, all the chips are heated and interconnected at once during MR-MUF. As the process simultaneously fills the protective material between the chips and packs the chip, it further increases the efficiency. In fact, SK hynix has seen a threefold improvement in productivity with this technology. For example, the 12-layer HBM3 improved heat dissipation by 36% compared to its predecessor.

This is how SK hynix developed its 24 GB 12-layer HBM3 that provides the largest capacity and highest performance, while maintaining the same thickness as its 16 GB 8-layer counterpart. Meanwhile, SK hynix also plans to advance its bonding technology and apply it to HBM products in the future. The company aims to strengthen its presence in the HBM market by developing new products through hybrid bonding, which interconnects data holes directly without bumps.

Taking Advanced Packaging Technology to the Next Level

In this episode of the Pathfinder series, we took a look at SK hynix’s advanced packaging technologies that innovatively solved the limitations of miniaturization. SK hynix has taken a step forward in the era of semiconductor convergence with advanced packaging technologies that include chiplets, MCP, VFO, and advanced MR-MUF, while actively developing products such as HBM, PIM, and CXL. More importantly, the company plans to even further enhance its advanced packaging technology to prepare for the upcoming era of heterogeneous integration.

<Other articles from this series>

[Tech Pathfinder] HKMG Opens the Door to Leading Mobile DRAM LPDDR5X & LPDDR5T

The post [Tech Pathfinder] Small Size, Big Impact: Unveiling the Latest Advances in Semiconductor Packaging and Miniaturization first appeared on SK hynix Newsroom.

From breaking barriers for performance with HBM3 to developing the world’s fastest mobile DRAM, LPDDR5T, SK hynix’s product portfolio is full of industry-leading solutions which have pushed technological limits. But how exactly does the company realize this rapid evolution in its solutions? What innovations and processes are applied to these products to take them to the next level?

To shed light on these technologies, SK hynix Newsroom is launching its seven-part Tech Pathfinder series. The articles in the series will introduce some of the company’s most advanced products globally renowned for their unprecedented qualities including industry-leading processing speed, data storage, and computational capabilities. Through the series, readers will gain a better grasp of the concepts behind these innovative products and gradually become more familiar with the advancement of semiconductors and technology in general.

SK hynix’s Secret Behind Its DRAM Development

In November 2022, SK hynix released a mobile DRAM with the world’s lowest operating power of 1.01-1.12V and an operating speed of 8.5 Gbps—Low Power Double Data Rate 5X (LPDDR5X). The company then made another historic step in January 2023 with the development of its Low Power Double Data Rate 5 Turbo (LPDDR5T), the world’s fastest mobile DRAM which offers an operating speed of 9.6 Gbps.

▲ Figure 1. SK hynix’s LPDDR5 Lineup Made With the HKMG Process

Smartphone mobile DRAMs need to be small, low-power devices which provide fast processing speeds to perform more functions. However, as the industry reaches the limits of scaling¹, such mobile DRAM technology only becomes more complex. So, what is the secret in SK hynix’s technology that has allowed the company to remain a powerhouse in mobile DRAM development? The answer lies in the world’s first application of the High-K Metal Gate (HKMG) process to mobile DRAM. This article will summarize the principle of the HKMG process and how this technology was applied to the LPDDR5X and LPDDR5T.

¹Scaling: The reduction in size of semiconductors to produce better device performance, power efficiency, and cost.

HKMG Process: Key to the World’s Fastest Mobile DRAM With Lowest-Power Consumption

▲ Figure 2. SK hynix Applies HKMG Process to Develop the World’s Fastest Mobile DRAM

Although HKMG was commercialized over a decade ago, various challenges were encountered during the development of this groundbreaking technology. There were four major obstacles: the extreme complexity of the technology, the high-processing cost compared to conventional materials, unpredictable risks, and the difficulty in controlling electron leakage. More importantly, the whole HKMG process had never been applied to mobile DRAM before. Despite facing these issues, SK hynix took on the challenge of changing the paradigm of mobile DRAMs.

More specifically, applying the HKMG process to mobile DRAM peripheral (peri) transistors posed a major challenge. DRAMs typically consist of cell transistors which store data and peri transistors which conduct data input and output. It is therefore necessary to minimize the impact of the HKMG process on the cell as the connection between the cell and peri transistor can encounter problems when applying the HKMG process to the periphery.

Accordingly, the area of the peripheral circuit that powers the cell is also reduced as the cell scale is minimized. This leads to a shrinking of the transistors that supply the charge, which, consequently, reduces the thickness of the gate insulator. These insulators for conventional mobile DRAMs are generally made from silicon oxide (SiON), which suffers from speed limitations when it is thinned. SiON also faces an efficiency problem as, when the thickness of the insulator decreases, the amount of leakage current increases and this leads to a loss in power.

SK hynix’s solution to these issues was to apply High-K material to the insulation film as the material has a permittivity² that is about five times higher than conventional SiON insulation film. To put this into context, when the same voltage is applied, the High-K insulation film can keep five times more charge than a conventional SiON material with the same area and thickness. This means that the thickness and leakage current can be reduced by making the insulation film with High-K material.

²Permittivity: Degree of how many electrons can be stored inside a gate.

However, the combined use of polysilicon (poly-Si)—applied in existing gates—and High-K materials increased the gate’s resistance, so a higher voltage is required and electrons slow down. To combat this, the poly-Si gate was replaced with a metal gate. With the combination of a gate oxide that possesses a high permittivity and a metal electrode, SK hynix successfully created an integrated HKMG solution.

▲ Figure 3. Description of HKMG Technology

Pioneering the Application of the HKMG Process

In preparation for the development stage, SK hynix first set up a taskforce comprised of device and process experts in the development, research, and manufacturing fields. The taskforce, the first of its kind for a derivative product³, consisted of members of the and PE (Product Engineering) team. Having begun working together from the initial stages of the process development, the taskforce resolved issues such as reliability and quality risks. Their main goal was to develop an integrated solution incorporating HKMG technology to the existing process while minimizing costs by maintaining parts of the existing process as much as possible.

³Derivative product: A product that is derived from a core product. Core products, a kind of prototype in which existing technology and elements are applied, allow manufacturers to establish a leadership position in the related technology as they can be quickly developed. The resultant derivative products feature various capacity and performance modifications to meet market needs.

It was also necessary to develop a method for utilizing the characteristics of the HKMG process to both increase speed and reduce power usage. However, due to the limitations in the chip’s size, lowering the electrical capacity to reduce power was not possible. Consequently, it became necessary to create a design that would lower the voltage. To this end, innovative design ideas were produced which eventually led to low-power solutions. These solutions included using a power architecture that would lower the design’s internal power and lowering the gate level in sleep mode to significantly reduce power consumption.

SK hynix Rewrites the Rules With LPDDR5X and LPDDR5T

▲ Figure 4. SK hynix’s World-First Application of HKMG Process to Mobile DRAM Enables Ultra-High Speed & Ultimate Power Efficiency

While effectively controlling leakage current, LPDDR5X offers a 33% increase in speed (8.5 Gbps) and a 21% power usage reduction compared to the previous generation. This increase in energy efficiency ensured the product reached its environmental goal of carbon reduction as well as meeting target technological specifications. Skip forward two months and LPDDR5T was developed. Operating in the same ultra-low voltage range as LPDDR5X, it is 13% faster at 9.6 Gbps to make it the fastest mobile DRAM available today.

SK hynix’s mobile DRAM which applies the HKMG process has been praised for its world-class performance. The company is also promoting the establishment of a new specification for mobile DRAM at the Joint Electron Device Engineering Council (JEDEC). SK hynix’s next step is to actively leverage the experience gained from the successful development of the HKMG process to bring even greater innovation to the next generation of technologies and products. In other words, LPDDR5X and LPDDR5T are just the beginning.

<Other articles from this series>

[Tech Pathfinder] Small Size, Big Impact: Unveiling the Latest Advances in Semiconductor Packaging and Miniaturization

The post [Tech Pathfinder] HKMG Opens the Door to Leading Mobile DRAM LPDDR5X & LPDDR5T first appeared on SK hynix Newsroom.