In February 2024, SK hynix became the first semiconductor company to unveil a mid- to long-term roadmap for bolstering the use of recycled materials. Through the roadmap, the company aims to raise the percentage of recycled materials used in its products to 25% by 2025 and to above 30% by 2030. The development of the neon recycling technology is expected to be a significant achievement for the company’s Material Recycling department in line with this roadmap.  

Figure 1. The process for recycling neon gas

Neon is one of the rare gases¹ and a key component of excimer laser gases², which are essential in the semiconductor lithography process³. As neon does not chemically decompose or transform when used as a laser light source, it can be recycled and reused through separation and purification processes. 

Taking advantage of this characteristic, SK hynix and TEMC succeeded in developing neon recycling technology. For the recycling process, a scrubber⁴ is used to capture the neon gas which is then collected in a tank following lithography. The neon gas is then selectively separated and purified using TEMC’s gas treatment process before being supplied to SK hynix for reuse in semiconductor manufacturing. Currently, the neon recovery rate, which is measured by multiplying emissions, capture volume, and purification yield, is at 72.7%. SK hynix plans to increase this rate to 77% by continuously improving the purification yield.

¹Rare gas: Gases including helium, neon, argon, krypton, xenon, and radon that exist in low concentrations in the atmosphere. Largely used in industrial processes, they are difficult to mass produce and impossible to synthesize artificially.
²Excimer laser gases: A mixture of noble, halogen and buffer gases used for an excimer laser, a type of ultraviolet laser used in lithography.
³Lithography: The process of creating patterns onto a substrate, typically silicon wafers, with a laser to define the layout of electronic components.
⁴Scrubber: Equipment that filters and treats waste gases generated during the semiconductor manufacturing process.

One-Team Collaboration with Partners Expected to Cut Neon Purchasing Costs

Figure 2. SK hynix collaborated with materials and equipment partners to recycle neon gas

SK hynix was able to develop this technology as a result of close cooperation and synergy with its materials and equipment partners which boast expertise in their respective fields. The company plans to develop more of these partnerships with industry specialists in the future.   

The application of the recycling technology offers significant benefits. When used in semiconductor fabs, the neon recycling technology is expected to cut the cost of purchasing neon by KRW 40 billion (USD 30 million⁵) per year⁶. 

⁵Based on the KRW-USD exchange rate in March 2024.
⁶This figure is based on the unit cost of neon in 2022 and expected volume that will be used in one fab of the Yongin Semiconductor Cluster.

The First Step to Developing 10 Raw Material Recycling Technologies by 2025

Figure 3. (From left to right) Hwanuk Song, Buseup Song, and Youngjun Jeong of the Material Recycling department discuss recycling innovations

The Material Recycling department led the development of the neon recycling technology. As a subcommittee of the Carbon Management Committee⁷, it is responsible for securing recycling technologies for non-chemically modified materials and establishing a recycling-friendly fab environment based on these innovations. The subcommittee aims to recycle all materials that are not chemically decomposed and transformed during the semiconductor process. By 2025, it plans to develop recycling technologies for a total of ten raw materials, including neon, deuterium, hydrogen, and helium gases, as well as chemicals such as sulfuric acid. Looking further ahead, the company aims to complete a technology review for all non-chemically modified materials by 2030. 

⁷Carbon Management Committee: A company-wide organization involving research, manufacturing, facilities, environment, and procurement to achieve net-zero emissions by 2050. The committee leads initiatives such as low-power equipment development, process gas reduction, and energy reduction based on AI/DT technology.

Figure 4. The five stages of developing recycling technology

To achieve these goals, the subcommittee has categorized the development of recycling technologies into five stages based on technological maturity. As shown in Figure 4, the subcommittee aims to reach stage 3 (material evaluation) for ten raw materials including neon by 2025.  

Ultimately, SK hynix plans to overcome the uncertain supply of materials which are largely imported from overseas, thereby elevating the company’s competitiveness for years to come.   

The post SK hynix Teams Up With Local Partners to Develop Pioneering Neon Gas Recycling Tech first appeared on SK hynix Newsroom.

Packaging With a Fully Intact Wafer

WLP refers to the process that is performed before the wafer is diced. It generally includes fan-in wafer-level chip scale packaging (WLCSP) and fan-out WLCSP in which the entire process is performed while the wafer is still fully intact. Nevertheless, redistribution layer (RDL) packaging, flip chip packaging, and through-silicon via¹(TSV) packaging are also generally categorized as WLP even if only a part of their processes are performed before the wafer is diced. Depending on which of these types of packages is used, there are variations in the type of metal and pattern formed by electroplating². However, they all follow a similar sequence during packaging as described below.

¹ Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

² Electroplating: A reaction where oxidation occurs at the positive plate to produce electrons which are transmitted to a wafer with a solution that has metal ions that are negative plates to become metal.

After wafer testing is performed, a dielectric layer is created on the wafers as needed. The dielectric layer then exposes the chip pad again, following the first exposure during testing, with photolithography.

Afterwards, a metal layer is applied on the surface of the wafer through sputtering³. This metal layer enhances the adhesion of the electroplated metal layer that will be formed and acts as a diffusion barrier to prevent the development of chemicals within metals. It also functions as a pathway for electrons during the electroplating process, and applies photoresist to create an electroplating layer while a pattern is created through photolithography. A thick metal layer is then formed by electroplating. When electroplating is completed, the next step is to proceed with the PR stripping process while the remaining thin metal layers are removed by etching. As a result, the electroplated metal layers are formed on top of the wafers in the desired patterns. This pattern serves as the wiring for fan-in WLCSP, the pad redistribution in RDL packaging, and the bumps in flip chip packaging. The following sections will take a closer look at each of these processes.

³ Sputtering: A process in which plasma ions physically collide with a target and removes the target’s material so it can be deposited onto the wafer.

▲ Figure 1. The steps involved in various wafer-level packaging processes

Photolithography: Sketching Patterns on a Masked Wafer

Photolithography, a combination of “-litho” (stone) and “graphy (drawing),” refers to a printing technique. In other words, photolithography is a patterning process in which a photosensitive polymer called a photoresist is applied to the wafer and selectively exposed to light through a mask that has a desired pattern on it. The areas that are exposed to light are developed, and the required pattern or shape is created. The sequence of this process is shown in Figure 2.

▲ Figure 2. The steps of photolithography

In WLP, photolithography is primarily used to form patterns on dielectric layers, to create an electroplated layer by photoresist patterning, and to create metal wiring by etching diffusion layers.

▲ Figure 3. A comparison of photography and photolithography

To understand photolithography more clearly, it will be helpful to compare it with photography. As shown in Figure 3, photography uses sunlight as its light source to capture a photo of its subject, which could be an object, landscape, or a person. On the other hand, photolithography requires a specific light source to transfer patterns on a mask to an exposure tool. Lastly, the role of the film in a camera is equivalent to the photoresist that is applied to a wafer during photolithography. Consequently, there are three methods to apply a photoresist on the wafer as shown in Figure 4. They consist of spin coating, film lamination, and spray coating. After applying the photoresist, soft baking is performed to remove solvents to ensure that the viscous photoresist remains on the wafer and maintains its thickness.

As shown in Figure 5, spin coating places viscous photoresist onto the center of a spinning wafer so the photoresist is spread towards the edges due to centrifugal force. This makes the photoresist form a uniform thickness on the wafer. If the viscosity of the photoresist is high while the spin speed is low, the photoresist will be applied thickly. Conversely, if the viscosity is low and the spin speed is high, it is applied thinly. In the case of wafer-level packages, especially flip chip packages, they require a photoresist layer with a thickness ranging from 30 to 100 micrometers (μm) to form solder bumps. However, it is not easy to achieve the desired thickness in a single spin coating. In some instances, it is necessary to repeat the application of photoresist and soft baking more than once. Accordingly, when a thick photoresist is required, it is effective to use lamination as it makes the film the desired photoresist thickness from the start. It is also more cost-effective because there is no waste from the wafer during processing. However, if there are rough surfaces on the wafer’s structure, it can be difficult to adhere the film to the wafer which can lead to defects. For wafers that have very rough surfaces, a uniform thickness of photoresist can be achieved through spray coating.

▲ Figure 4. The three methods to apply photoresist

▲ Figure 5. An overview of spin coating

After the photoresist is coated and soft baked, the next step is to expose it to light. By shining light through a pattern formed on the mask, the photoresist on the wafer receives the image of the pattern. When using a positive photoresist that weakens when exposed to light, the mask needs to have holes in areas that are going to be removed. However, when using a negative photoresist that hardens when exposed to light, the mask must have holes in the areas that need to remain. For WLP, a mask aligner⁴ or a stepper⁵ is typically used as the process equipment for photolithography.

⁴ Mask aligner: One of the exposure tools that aligns the pattern on the mask and the wafer so that light can pass through them simultaneously.

⁵ Stepper: A machine where the stage moves in steps and photolithography is performed by a shutter that opens and closes to allow light to pass through.

Development is the process of dissolving the parts of the photoresist that have been weakened through photolithography with a developer solution. As shown in Figure 6, there are three types of development: puddle development that pours the developer onto the center of the wafer so it spins at a low speed, tank development that immerses multiple wafers in the developer at the same time, and spray development that sprays the developer onto the wafer. Figure 7 shows an overview of a chamber for puddle development. After the puddle development is finished, the photoresist takes on the desired pattern through photolithography.

▲ Figure 6. Three different methods of development

▲ Figure 7. An overview of a chamber for puddle development

Sputtering: Forming Thin Films on the Wafer

The process of sputtering is a type of physical vapor deposition⁶ (PVD) that forms a thin film of metal on a wafer. If the metal film formed on the wafer is below the bumps as seen in flip chip packages, it is called an under bump metallurgy (UBM). Typically, it is in the form of two or three layers of metal film, including an adhesion layer, a current carrying layer that provides electrons during electroplating, and a diffusion barrier with solder wettability⁷ that suppresses the formation of compounds between the plating layer and the metal. If the layers are comprised of titanium, copper, and nickel, the titanium acts as the adhesion layer, the copper acts as the current carrying layer, and the nickel acts as the diffusion barrier. Accordingly, the UBM has a significant impact on the quality and reliability of flip chip packages. As for metal layers like an RDL and a WLCSP that are used to form metal wiring, they usually consist of an adhesion layer and a current carrying layer that improves adhesion.

As Figure 8 shows the sputtering process, it starts with argon gas transforming into plasma⁸ and colliding with a target that has the same composition as the metal on which positive argon ions will be deposited. The impact of the collision removes the metal particles from the target so they are deposited on the wafer. The metal particles deposited by sputtering have a consistent directionality. Even though a flat plate is deposited with a uniform thickness, plates in the shape of a trench or vertical interconnect access (via) can have different results. Such irregular shapes can make the deposition thickness of the wall’s surface that is parallel to the metal deposition become thinner than the plate’s floor that is perpendicular to the metal deposition.

⁶ Physical vapor deposition (PVD):  A process used to produce a metal vapor that can be deposited on electrically conductive materials as a thin and adhesive pure metal or alloy coating.

⁷ Wettability: The phenomenon where a liquid spreads on the surface of a solid due to the interaction between the liquid and the solid surface.

⁸ Plasma: A state of matter that is electrically neutral due to the coexistence of freely moving protons and electrons. When heat is continuously applied to a gaseous substance to raise its temperature, a collection of particles consisting of ions and free electrons is created. It is also called the “fourth state of matter” in addition to solid, liquid, and gas.

▲ Figure 8. The fundamentals of sputtering

Electroplating: Forming Metal Layers to Bond

Electroplating is the process of depositing metal ions of an electrolyte solution as metal on a wafer. This is possible through a reduction reaction using externally supplied electrons. In WLP, electroplating is used to form thick metal layers such as metal wiring for electrical connections or bumps for junctures. Just as Figure 9 illustrates, a metal undergoes oxidation at the anode to become an ion and releases electrons to the external circuit. The metal ions oxidized at the anode or present in the solution receive electrons and undergo a reduction reaction to become metal. In the electroplating process for WLP, the cathode plate becomes the wafer. The anode plate is made of the metal to be plated, but it also uses an insoluble electrode⁹ such as platinum. If the anode plate is made of the metal to be plated, metal ions are dissolved from the anode plate and continuously distributed to maintain a consistent ion concentration in the solution. However, if an insoluble electrode is used, metal ions expended while being plated on the wafer must be periodically replenished in the solution to maintain the ion concentration. Figure 10 below shows the electrochemical reactions that occur at the cathode and anode, respectively.

⁹ Insoluble electrode: An electrode used primarily in electrolysis and plating. It is neither chemically nor electrochemically soluble. Materials such as platinum are used for its creation.

▲ Figure 9. The process of electroplating

▲ Figure 10. Electrochemical reactions at the cathode and anode expressed as formulae

The equipment that electroplates a wafer is typically placed so the side of the wafer to be plated faces down while the anode is positioned below the solution. Electroplating happens when the solution flows toward the wafer and forcefully collides with the surface. At this point, patterns formed from photoresist can come into contact with the solution on the parts of the wafer to be plated. Electrons are distributed through the electroplating equipment at the edge of the wafer and eventually meet the metal ions in the solution at the patterned parts. They then combine with metal ions inside the solution where the patterns are formed to go through a reduction reaction and grow to form metal wiring or bumps.

PR Stripping and Metal Etching: Removing the Photoresist

Once the processes that use the photoresist pattern are complete, the photoresist must be removed via PR stripping. PR stripping is a wet process that uses a chemical solution called a stripper, and implements development methods such as puddle, tank, or spray. After a process like electroplating forms metal wiring or bumps, the metal film formed by sputtering must also be removed. This is necessary as the entire wafer will be electrically connected and result in a short circuit if the metal film is not taken off. The metal film is removed by wet etching with an acid-based etchant that can dissolve the metal. While the technique is similar to PR stripping, puddle development has been used more widely as metal patterns on the wafer have become finer.

A More Efficient and Reliable Packaging Process

WLP strives for efficiency, miniaturization, and reliability through the above mentioned stages that begin with sketching patterns through photolithography and culminate in removing the applied photoresist through PR stripping. The next episode will look into the different types of WLP that use technologies such as fan-in and fan-out WLCSP, RDL, flip chip, and TSV.

Read articles from the Front-End Process series

Read articles from the Back-End Process series

The post Semiconductor Back-End Process Episode 7: The Wafer-Level Packaging Process first appeared on SK hynix Newsroom.

Just Like Baking Cookies

The emergence of the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) allowed more transistors to be packed into a fixed space. As MOSFETs became smaller, they were able to use less power while obtaining more functions as the number of transistors increased. Consequently, making MOSFETs smaller is essentially killing two birds with one stone and proves to be critical to the development of semiconductors.

The process for manufacturing semiconductors shares similarities with baking cookies. Imagine making a batch of cookies in the shape of SK hynix’s “Wings of Happiness” logo. It would take a very long time to make hundreds of these cookies by hand. So, what are the alternative options?

▲ Figure 1: How to swiftly make cookies in the same shape

The best solution would be to use a cookie cutter on the dough. This makes baking 100 cookies relatively simple. But what if the cookies needed to be made smaller? Then, a cookie cutter with a smaller shape could be used to create the cookies. The role that cookie cutters play is similar to the role that the machine called a “stepper” plays in semiconductor manufacturing. The difference between MOSFETs and cookies, nonetheless, is that people prefer MOSFETs that are small and tightly packed, as having two small MOSFETs is much more useful than having one large one.

The process of producing semiconductors is similar to the steps described above. However, the process becomes more complex when the wing-shaped cookies need to be colored.

▲ Figure 2: The order of coloring the wing-shaped cookies

▲ Figure 3: Cookies can be quickly sprayed with color when they are bunched together

By following the steps shown in Figures 2 and 3, color can be added to the cookies. After cutting the cookies into the desired shape, the areas that don’t need to be colored are covered before the whole surface is sprayed with pigment. This method allows one to bake cookies with a specific shape or color in a short amount of time. But this still doesn’t explain how the black cover in the above image is made. This is, in fact, the main function of the process called “exposure.” While the cookies in the images above only have two layers of color, semiconductors require dozens of layers that begin from the device layer to multiple metal line layers. This is why exposure becomes such an essential process.

Photolithography: The Process of Making Semiconductor Patterns

In the semiconductor industry, the process of applying the pattern of a cookie to a wafer is known as photolithography. One of the first steps in this process is to apply a light-sensitive solution called a “photoresist” which changes properties when exposed to light. After applying the photoresist, light (laser) is shot at the wafer so the areas covered in the photoresist can be printed with the required pattern.

▲ Figure 4: The general sequence of photolithography

To ensure that only the desired areas of the wafer are exposed to the light, a disc with the required pattern is placed in front of the light. This disc is called a “photomask.” The intended pattern is printed on top of the wafer by shining light through the photomask and onto the wafer.

Once the pattern is created, it goes through the “develop” process which will later be explained in more detail. As areas covered with the photoresist are removed with exposure to light, a stamp with the desired pattern is created.

Selecting Positive or Negative Photoresists

There are two types of photoresist used in the photolithography process: positive or negative photoresist. A positive photoresist softens when it is exposed to light making it more soluble when the solvent is applied, while a negative photoresist will harden when exposed to light and remain on the wafer. With a positive photoresist, the areas exposed to light are removed during the develop process. Conversely, the areas not exposed to light are protected by the photoresist and are not removed during the develop process or the subsequent processes of etching and deposition.

Semiconductor manufacturers choose the type of photoresist according to the purpose of the process. For example, a negative photoresist is not suitable for making fine patterns because the hardened areas that were exposed to light will absorb some of the solution during the develop process and start to swell up. That’s why a positive photoresist is usually used when making fine patterns. On the other hand, a negative photoresist holds the advantage of being cheaper and yielding a higher resistance to processes like etching.

▲ Figure 5: Positive and negative photoresists

After choosing which photoresist method to use, a device called a “coater” is used. When drops of photoresist fall on the wafer, the coater spins rapidly and spreads the photoresist evenly. After applying the photoresist, manufacturers remove excess photoresist found on the back or edges of the wafer. They also evaporate excessive soluble components by heating them inside an oven, all the while preparing for the next stage of the process.

Over time, the structure of photoresists has become more complex. Photoresists usually consist of multiple layers, and one of these layers is called the bottom anti-reflective coating (BARC). It was developed as the need for miniaturization grew and as light from the stepper started to reflect off the wafer and affected the formation of patterns. The BARC is a substance that is applied to the wafer’s surface before applying the photoresist to prevent the reflection of light (hence the name “bottom,” as it’s located under the photoresist). Additionally, with the development of lithography systems that use water (ArF immersion¹), a waterproof coating called the top anti-reflective coating (TARC) was developed to repel water droplets and prevent damage.

Rather than memorizing every structural detail of a photoresist, it’s more helpful to examine how the industry has addressed new challenges it has faced when new technologies were introduced. Problems that surfaced after using an extreme ultraviolet (EUV) stepper² are a good example. After an EUV stepper was used, high-energy EUV rays hit the photoresist and rebounded back, resulting in the contamination of the photomask. The problem was only solved with research on photoresist materials and by introducing a protective film on photomasks called a pellicle.

¹ArF immersion: An argon fluoride (ArF) immersion stepper that uses water instead of air as the medium for light, improving its performance.
²EUV stepper: A machine that makes ultra-fine patterns using extreme ultraviolet rays.

Creating the Pattern Outline with Photomasks

▲ Figure 6: Operation of a stepper

After applying the photoresist, patterns are drawn on top of it. In order to create the desired pattern on the photoresist, a transparent plate containing the pattern called a photomask is needed. The photomask is largely opaque with some transparent areas to allow light to pass through. As the name suggests, the photomask is placed between the light source and the wafer to create the required pattern. The pattern on the photomask is designed taking into account possible issues such as light interference, so it might look different from the pattern that the manufacturer originally intended to make.

The pattern on the photomask is essentially the design of the semiconductor and, consequently, determines its usage. Photomasks used in semiconductor memories such as DRAM and NAND flash have very regular and repetitive patterns that are hard to see with the naked eye. On the other hand, photomasks used for making logic semiconductors such as CPUs and GPUs have very complex patterns.

Additionally, semiconductor manufacturing requires multiple photomasks. After using a photomask for exposure, various processes like etching, deposition, and oxidation are performed. Then, the above processes are repeated to build up the next layers. Ultimately, the design process involves creating photomasks for each layer of a semiconductor in order to provide the semiconductor chip with the desired function of the manufacturer.

Since the photomasks are prepared in advance, the next step is to accurately find the starting position for exposure. This operation is called alignment. As for exposure, it can be performed multiple times in semiconductor manufacturing. And since the patterns on a semiconductor are only tens of nanometers apart, small errors can accumulate and, thus, cause large defects. Such problems can be prevented before carrying out exposure by precisely adjusting the array according to the alignment mark produced in the previous process.

Exposure and Refining Patterns with Steppers

The stage where light is actually shone onto the wafer is called exposure. Light, or a laser, is shone onto a small area of the wafer that’s the size of a chip. After a certain amount of time, the stepper moves slightly to the side of the wafer and repeats the process.

The capability of the stepper to distinguish between two objects and analyze them is called “resolution.” Resolution is conveyed by the following formula: d=λ/(2NA) (where λ is the wavelength of light and NA is the numerical aperture). If the resolution is high, two nearby objects may seem as one. So, no matter how fine the pattern on a photomask is, the pattern is not etched accurately on the wafer’s surface.

Therefore, the key is to reduce resolution, and the light’s wavelength is the most important factor when reducing resolution. As the energy of the laser increases, the wavelength of the light decreases. The EUV stepper is a machine that can draw finer patterns than a deep ultraviolet (DUV) laser by reducing the wavelength by 1/14, or increasing the energy of the light. Another way to improve resolution is to increase the numerical aperture (NA). The NA can be increased by making the lens of the light source larger or by using a medium with a high refractive index. An example of the former is High NA EUV while DUV (ArF immersion), which is still commonly used, is an example of the latter.

The NA is a measure that may be difficult to understand initially. This concept can be clarified by referring to Figure 7 below, which shows that resolution improves, or decreases, when the lens of the light source becomes larger.

▲ Figure 7: Numerical aperture and resolution

Finding a suitable light source for the stepper is very difficult. In the early 2000s, researchers were able to discover a better light source, but it took over 10 years to commercialize a 13.5nm light source for EUV after developing the argon fluoride (ArF) 193nm laser. This is due to shorter wavelengths of light being less refracted and more likely to be absorbed when they hit a material. This is why the development of EUV steppers has been the subject of intense debate among semiconductor manufacturers.

Exposure is also critical for achieving high yields in semiconductor manufacturing. As explained earlier, exposure cannot be performed on multiple wafers at once—unlike oxidation. Thus, it’s impossible to create a uniform light source that can process a wafer with a 300mm-wide diameter. The latest steppers are very expensive, costing over 76.8 million US dollars per unit. Nevertheless, they can only process about 100 wafers per hour. The money invested in exposure itself is 12 times as much as the money spent on oxidation. For EUV, it was much harder to achieve commercially meaningful throughput than it was to create a light source. To solve this problem, the materials sector also had to work hard to find a photoresist material that would still react strongly to less light.

Once exposure is complete, overlay may be performed. Overlays are small marks placed on the wafer during the exposure process. If an overlay mark is engraved in a shape that shares the center and varies in size at every exposure, it becomes possible to measure how misaligned the exposure is or whether the wafer is slightly rotated. However, unlike the alignment process, overlay measurements are not performed on all wafers.

The Develop Process and Finalizing the Pattern

After light is shone on the photoresist, the areas that were exposed to the light either soften or harden depending on if a positive or negative photoresist was used, respectively. This process is called develop, and it involves removing the parts of the wafer that were exposed to the light.

Before this process, the wafer is heated again in an oven during a process called post-exposure bake (PEB). This helps to further intensify the changes in the photoresist that was exposed to the light.

Once the develop process is complete, a chemical agent known as a developer is applied to remove the areas of the photoresist that were affected by the light. Depending on the material used for the photoresist, the area may be rinsed. The solution used for rinsing differs according to the substance used for the photoresist. The rinsing equipment can also vary, and the choice of equipment often has a trade-off relationship between the processing speed and the rate of defects.

After the photoresist has been properly processed, the semiconductor frame is finally ready to be used. Transistors and wires can then be made by applying photomask on the photoresist that’s on top of the wafer or by carving out the desired parts.

The Development of Photolithography and Holistic Thinking

The photolithography process illustrates how important it is to have a deep understanding of the underlying technology rather than merely memorizing specific details. When the ArF laser’s light source reached its limit at 193nm, EUV technology wasn’t ready yet. But since microfabrication had to continue, industry professionals developed ArF immersion equipment to reduce the wavelength of the same light source. This allowed the semiconductor industry to approach processes below 100nm. Achieving this feat required contributions from other sectors.

▲ Figure 8: New technology added for the ArF immersion equipment

To use the immersion equipment, the wafer must be covered with a liquid that has a high refractive index—or water. However, this poses challenges as the semiconductor process is so advanced that even small errors can cause problems. Impurities in the liquid can cause defects in the semiconductor or photoresist and can even dissolve the photoresist over time. To address these issues, it’s necessary to develop technologies that produce high-purity water and to apply a protective coating that can be easily removed from the photoresist. Since the coating changes the properties of the photoresist, changes are also required in the develop process.

These challenges are something that the semiconductor industry and its professionals will have to work together to solve. Recently, SK hynix collaborated with a materials company to develop a dry photolithography process.

As explained in the previous article that focused on the process of oxidation, a dry process is a process that doesn’t involve water. Unlike the immersion method described above, the dry process involves attaching the photoresist directly to the wafer and not rinsing it during the develop process. Among the numerous reasons for developing these new technologies, the most important is that miniaturization has advanced to the extent that fine patterns are damaged in the process of applying and cleaning the photoresist even when the stepper shines light with a small photomask. Such challenges will continue to appear down the road, but the semiconductor industry will keep coming up with innovative solutions to combat them.

Photolithography is Just One Step

After a pattern has been successfully created using photolithography, the next step is to fill or carve off the insides of the pattern. While photolithography is one of the crucial processes of semiconductor manufacturing, it’s not the only important one. Creating a fine pattern through photolithography is only one step, as utilizing it for a specific purpose is a completely different story.

Read articles from the Front-End Process series

Read articles from the Back-End Process series

The post Semiconductor Front-End Process Episode 3: Forming Patterns on Wafers Through Photolithography first appeared on SK hynix Newsroom.

SK hynix now ​maintains a stable supply of neon gas despite the unstable international market, and is able to significantly reduce purchasing costs. The company aims to use 100% of locally produced neon gas by 2024.

Until now, Korean semiconductor companies have relied solely on imports of neon gas. In recent years, neon prices have been soaring as the international situation in major overseas production regions has become disrupted. In order to address the risk of supply instability, SK hynix has collaborated with Korean partners TEMC, a semiconductor gas manufacturer, and steelmaker POSCO, to produce the gas domestically.

A large air separation unit (ASU) plant is required to extract neon, which is rare in the air, resulting in a high initial investment. In response to SK hynix’s objective to procure neon locally, TEMC and POSCO collaborated to develop a technology for producing neon at a low cost by utilizing existing facilities. SK hynix evaluated and verified the locally produced neon and succeeded in using it in the semiconductor manufacturing process earlier this year. The neon is produced by POSCO, processed by TEMC, and then supplied to SK hynix as a top priority.

Neon is the main component of excimer laser gas used in semiconductor photolithography . The excimer laser gas produces a short wavelength ultraviolet laser light that engraves electric circuits onto wafers. Although 95% of the excimer laser gas is composed of neon, neon is a rare gaseous element that makes up only 0.00182% of the air.

SK hynix introduced locally produced neon to semiconductor photolithography in April this year for the first time in the domestic semiconductor industry, increasing its use to 40% of all neon used in the manufacturing process. By 2024, all of SK hynix’s semiconductor manufacturing will use locally produced neon.

In addition, to reduce the risk of raw material shortages, SK hynix plans to procure krypton and xenon gas locally by June 2023 both of which are used in the etching process^* of semiconductors. As a leading global technology company, it plans to continue securing the resources necessary for the development of advanced semiconductor technologies.

^*Etching process: the process of removing unnecessary parts on the exterior of the circuit engraved on the wafer through photolithography.

“Cooperation with domestic partners greatly contributed to stabilizing supply in spite of an uncertain market due to the unstable international situation. We plan to strengthen the semiconductor raw material supply chain through continuous cooperation with our partners,” said Hongsung Yoon, Head of FAB Materials Procurement at SK hynix.

The post An Industry First: SK hynix Sources Neon Gas Locally, Increases Its Use in Chip Production to 40% first appeared on SK hynix Newsroom.

“Moore’s Law is dead” – Semiconductor scaling hits a dead end

In semiconductor scaling, existing ‘multi-patterning’ is now unavailable courtesy of argon fluoride (ArF) lithography technology exposing its limitations on the newly adopted 10nm scale. In the semiconductor industry, ‘Moore’s Law’ stated that chip density doubles every 24 months. It held strong for a while but now faces its end due to the higher difficulty of photolithography processing.

Semiconductor production requires a photolithography process in which a thin yet powerful laser beam prints meticulous micro-circuit patterns onto a wafer, similar to how a photo is printed–which is why it is called ‘photo.’ ‘Photolithography’ is a technology which transfers and copies the shadows created by lighting a ‘mask’, or an original glass plate with metal patterns of the desired circuit design. This is one of the most crucial steps of the entire manufacturing process as these patterns are imprinted onto the wafer, with the accuracy of the circuit’s design ultimately determining its competitiveness in the market.

‘Scaling’ represents the industry’s supreme task, shortening the gate length within a transistor on a semiconductor circuit. The gate acts like a bridge between a source and a drain, controlling the flow of the current. Thus, as the gate length decreases, the amount of electron movement from a source to a drain increases accordingly, which in turn accelerates the circuit’s operating speed.

Semiconductor lithography equipment has seen many advances over the years, adopting a large lens with high numeral aperture (NA) or using short wavelength light as the light source. However, as gate length decreases below 30nm, the patterning ability of existing liquid immersion ArF lithography equipment reaches its limit. Whilst a multi-patterning method was applied for DRAMs of up to 18nm, this created additional processing stages and prompted productivity loss and increased material costs, which all resulted in escalating production costs. As the number of processing steps reached nearly 500 to 600, the only solution was painting minute circuit patterns with a ‘thinner brush,’ via the application of even shorter wavelength light.

Pioneering EUV technology could lead the way

Accordingly, the semiconductor industry has been preparing for new semiconductor lithography under the name EUV to enable 10nm-class scale processes. Dutch company ASML has a monopoly on EUV equipment and each unit costs between about USD 81 million and USD 122 million. By utilizing the light of a 13.5nm wavelength, much shorter than existing ArF wavelength of 193nm, EUV allows much finer semiconductor circuit patterns without multi-patterning. Through this, the number of processing steps is reduced and thus manufacturing time shorter than current multi-patterning, such as Quadruple Patterning Technique (QPT), giving EUV pioneering status as the only breakthrough to date.

However, applying EUV to chips like DRAMs is a challenging process requiring the most advanced technology around. For this reason, the industry is keeping a close eye on the yield of the DRAMs that are mass-produced by EUV for the first time. Regarding DRAMs, it is expected that EUV will be partially used in 2020 in manufacturing chips of 1ynm or smaller.

Image Download

Resolving technological challenges in EUV processing is the key

Resolving the technological challenges of EUV processing is vital for the future of the industry. EUV has a unique characteristic of being absorbed by nearly every matter, even gases. Therefore, it is necessary to develop new technologies first over the whole range of lithography process, including a new mask, photoresist, and optical systems. It is crucial to manufacture masks with no defects and to ensure developing new mask test equipment as well.

Increasing the number of wafers produced per hour is another important challenge. In 2018, ASML achieved a wafer per hour (WPH) of more than 125 and is aiming to break the 155 mark in 2020. In terms of light source output, it is known that DRAM manufacturers’ tests results showed up to 250W. Semiconductor manufacturers which started developing EUV processes with equipment bought from ASML are now at developing and testing the overall equipment. The industry is conducting research on high-NA processes of 0.55NA as the next-generation of lithography technology, beyond the 0.33NA currently being developed.

“For the successful mass-production of EUV lithography technology, securing technologies to manufacture EUV masks that assure zero defects, as well as hardware within lithography equipment, light sources and pellicle, is essential,” said an official from the semiconductor industry. “Research on a variety of technologies that test for defects within EUV masks is currently ongoing. For improved resolution, utilizing the light source of shorter wavelengths and securing higher NA are crucial.”

The post EUV Technological Innovation Shapes the Future of Semiconductors first appeared on SK hynix Newsroom.