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With the increasingly fiercer competition for scaling in the semiconductor industry, the photo process for printing fine circuit patterns on wafers is emerging as one of the most crucial processes. SK hynix is also making efforts to lead technology in this field, by introducing the extreme ultraviolet (EUV) lithography for DRAM mass production.

Our newsroom met with the members of the Photo Technology teams under the Manufacturing & Technology unit at SK hynix to have a glimpse of their job and the talents they seek to hire.

Mission: Win Yield, Productivity, and Cost Competitiveness

The top three priorities for semiconductor manufacturing and mass production are yield, productivity, and cost competitiveness. That sums up to a process of providing quality products with strong price competitiveness to customers at a right time. SK hynix’s Manufacturing & Technology unit is striving to constantly improve the three factors to remain the leader of the industry.
The semiconductor memory industry has been focusing on developing scaling technology that decreases the critical dimension (CD) of circuits and stacking semiconductor components to increase storage capacity and improve performance. Such efforts have brought the level of scaling down to 1/10,000 the thickness of a human hair, making further technological advancements challenging. The Moore’s Law that the density of semiconductors doubles every 18 months is believed to be no longer valid.

As a new strategy for scaling, an increasing number of semiconductor memory manufacturers are adopting the EUV lithography technology in the photo process where circuit patterns are printed onto wafers. With a short wavelength of around 13.5 nanometer, EUV equipment demonstrates excellent resolution¹, facilitating exposure of fine patterns. Also, by helping streamline the process, it also results in better cost competitiveness.

The Photo Technology teams under SK hynix’s Manufacturing & Technology unit are seeking various options to address the challenges for further scaling. The teams have been working to define a product’s process difficulty and requirement specifications in advance and develop the necessary technologies either on its own or through cooperation with business partners. They also work closely with the R&D division to preemptively reflect any possible challenges to mass production in advance to find a solution at an early time.

For photo process, two teams – Icheon DRAM Track Photo Technology and Scanner Photo Technology Teams – are responsible for securing and maintaining the best conditions for patterning, which is essential for high-quality products.

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The photo process is to imprint an identical shape and size of a designed semiconductor pattern onto a desired location of a wafer. The process mainly comprises of the three steps – photo resist (PR) coating, exposure, and development. The PR coating and development steps involve track equipment, while scanner is used for the exposure process.

The Track Photo Technology Team and Scanner Photo Technology Team are responsible for the operation and improvement of track equipment and exposure equipment, respectively. They’re also responsible for addressing the issues arising from the photo process or equipment.

“No Easy Answers…Curiosity Is the Key”

The newsroom met with the junior members of the Icheon DRAM Track Photo Technology Team and Icheon DRAM Scanner Photo Technology Team to hear about the competencies and qualities required for their work.

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Q. Please tell us about your job.

Young-joo Lee, a Technical Leader at Icheon DRAM Track Photo Technology team: I manage the data measured during the process at the Track Photo Technology Team. Matching the data with the equipment data and identifying the correlation with the sub-processes are also my responsibilities. I am also involved in development of the derivative products.

Sang-gwon Lee, TL at Icheon DRAM Track Photo Technology team: As an engineer of the team, I mainly manage yield, quality, and productivity. I am also responsible for the audits of the fab clients.

Q. Could you introduce some competencies your job requires?

Young-joo: Development of a new device is no longer bound to the responsibilities of the R&D division as the Manufacturing & Technology unit is also increasingly involved nowadays, making deep understanding and collaboration with different teams extremely important factors. Good communication skills are a must and a detail-oriented thinking is definitely a plus.

Sang-gwon: A good engineer should be able to handle the response parameter well if he/she is in charge of yield and productivity management. That means the engineer should have a good knowledge of the equipment principles that could affect the response. Also, since manufacturing & technology work cannot be done alone, good communication skills are wanted for collaboration with different teams handling other processes that can affect the photo process.

Q. What challenges have you encountered and how did you overcome?

Young-joo: Due to the high level of pattern shrink, managing overlay² is not easy. Semiconductors have a stacked structure, and managing overlay involves aligning the patterns formed on the upper and lower layers by using scanner equipment and numerically checking and correcting misalignments. We are now developing a system that can manage overlays in the mid- to long-term. Also, the previous method where human performed according to a manual is being replaced by automatic correction system.

Sang-gwon: For overlay management, we see an improvement, though. In the past, confirming any issues was possible at the state of mass production, but nowadays, thanks to the big data-driven system, we can figure them out beforehand. Also, overlay modeling, which once required direct measurement, can be done virtually now, helping us save time and improve the overlay management at the same time.

Q. What’s the atmosphere of the team like?

Sang-gwon: The fab runs 24 hours a day and accordingly, the workload is never light. This work can’t be done if without mutual consideration and support. The overall work environment is steadily improving thanks to a better system for cooperation and flexibility of the work coordination.

“Attractive Challenges…Stacking Layers of Experiences”

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Q. Please tell us about your job.

Seung-ho Lee, TL at Icheon DRAM Scanner Photo Technology team: Of the two main tasks of the scanner photo technology team, I am in charge of the process-related part. I analyze all the data generated from the process and the equipment and predict their impacts to finally find solutions.

Jae-won Lee, TL at Icheon DRAM Scanner Photo Technology team: I’m involved in the task of improving the scanner equipment. I focus on how to improve the productivity of the equipment, operate the equipment better and potential improvements of other key components including the photo wafer tables.

Q. Could you introduce some competencies required for the work?

Seung-ho: Ability to understand the data flow and predict a likely outcome is particularly important for the scanner photo-related work. Reading the correlation between the source data coming from the equipment and the response data is also important. Take the scanner, for example. A single wafer goes through various processes and tools during the photo process, so, you should pay a lot of attention on how equipment operation process affects the patterning.

Jae-won: This job requires a massive volume of knowledge ranging from optics, materials, chemistry, machinery to production & manufacturing engineering. Ability and willingness to learn related work extensively beyond your area is important.

Q. What challenges have you faced and how did you overcome?

Seung-ho, Jae-won: It is sometimes difficult to understand the invisible nano-scale world and solve the issues with technology. Meeting two contradictory core values at the same time is challenging, but interesting. For example, increasing production output and improving quality could be conflicting, but you should be able to meet them all. ‘I’m wanted because it’s difficult to solve’ is the mindset I try to keep whenever I encounter challenges.

Q. What are the fascinating aspects of your work?

Seung-ho: Being able to control the micro-processing of 1 to 2 nm levels itself is fascinating. We often say, in a joke, that controlling the overlay of 2 nm on a 300 mm wafer might be like intercepting a 0.0025 mm target by a fighter jet flying at Mach 3 speed.

Jae-won: The more experience and knowledge you accumulate over time, the greater influence you’ll have on your work. It is also great to touch a broader range of work than others and have more opportunities to indirectly experience various fields through cooperation. Above all, the experience of dealing with hundreds of equipment and people is something you could hardly expect from other teams.

¹Resolution: The ability to distinguish two adjacent objects as two different items; the higher the resolution, the finer the exposure equipment can form a circuit pattern.
²Overlay: Alignment status of the top-to-bottom alignment of stacked circuit patterns

The post Bringing Hyperscale onto the Wafers: Photo Technology Team first appeared on SK hynix Newsroom.

1. Aspect Ratio (A/R)

Figure 1. Concept of aspect ratio and changes in aspect ratio in accordance with technological advancement

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Aspect Ratio (A/R) is the ratio of the horizontal axis length compared to the vertical axis (height divided by width). As the critical dimension (CD) of a circuit gets smaller, the A/R value increases. That is, if the width is 10 nm when the A/R is 10, a hole with a 100 nm height should be dug out in the etching process. Therefore, for next-generation products requiring ultra-miniaturization (2D) or high density (3D), an extremely high A/R should be achieved to allow cations to penetrate the lower layer during etching.

To implement ultra-miniaturization technology with a CD less than 10 nm in 2D, the capacitor A/R of DRAM should be kept above 100. Likewise, the 3D of NAND flash also requires a high A/R to stack 256 layers or more of cells. Even if the required conditions of other processes are met, the necessary product cannot be produced unless the etching process supports it. This is why etching technology is becoming more important.

2. Overview of Plasma Etching

Figure 2. Plasma source gas by film type

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When a tube is hollow, the narrower the diameter of the tube is, the easier it gets for the liquid to enter due to the capillary phenomenon. However, it gets rather difficult if you have to dig out a hole (dead end) in the bare ground. For this reason, since the mid-70s when the circuit CD was 3 to 5 ㎛, dry etching became the trend, replacing wet etching. That is, although ionized, it is much easier to penetrate deep holes since the volume of individual molecules is smaller than that of organically agglomerated solution molecules.

In plasma etching, the inside of a process chamber where etching is to be performed should be first made into a vacuum state, before a plasma source gas suitable for the layer is injected. When etching a solid oxide film, a strong C-F-based source is used. For silicon or metal films, which are relatively weaker, a CL-based source gas is used.

Then, how should the gate layers and the underlying silicon dioxide (SiO2) insulating layers be etched?

First, in the case of gate layers, silicon is removed with a CL-based plasma (Si+ Cl2) with an etch selectivity of polysilicon. For the lower insulating layer, a two-step etching is performed with a more powerful C-F-based source gas (SiO2+CF4) with the selectivity to etch the SiO2 film.

3. Reactive Ion Etching (RIE, or Physicochemical Etching) Process

Figure 3. Strengths of RIE method (anisotropy and high etch rate)

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Plasma contains both isotropic radicals and anisotropic cations at the same time, then how does it perform anisotropic etching?

Dry etching using plasma is mostly performed in the reactive ion etching (RIE) method or an application based on the RIE method. The core of the RIE method is to weaken the binding force between the molecules of the target in the film by attacking the etching area with anisotropic cations. The weakened area is absorbed by radicals, combined with the particles constituting the layer to make them into a gas, which is a volatile compound, and release.

Although radicals are isotropic, molecules that make up the bottom surface, whose bonding force is weakened by the attack of cations, are more easily captured by radicals and turn into new compounds, than the walls with a strong bonding force. Therefore, downward etching becomes the mainstream. The captured particles turn into a gas with the radicals and are desorbed from the surface and released by the force of vacuum.

At this time, when physicochemical etching is performed by combining cations acting physically and radicals reacting chemically, the etch rate (etching degree over time) increases by 10 times compared to the case of performing cation etching or radical etching separately. With this method, the etch rate of the anisotropic downwards etching increases, resolving the issue of the polymer remaining after etching at the same time. This method is called RIE etching. The key to a successful RIE etching is to find the right plasma source gas suitable for the film to be etched. Note: Since plasma etching is RIE etching, they can be considered as the same concept.

4. Etch Rate and Core Performance Index

Figure 4. Core etching performance index related to the etch rate

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The etch rate refers to the depth of a hope when etching a film for one minute. Then, what does it mean that etch rates of various parts on a single wafer are different from each other?

This means that the depth of etching is different for each point on the wafer. For this reason, it is important to set the end of point (EOP) where etching should be stopped by considering the average etch rate and the depth of etching. Even when an EOP is set, there are still areas that are overly etched (over-etching) or insufficiently etched (under-etching) than planned. In etching, however, over-etching causes less damage than under-etching. This is because the less etched part in the case of under-etching hinders the following process such as ion implantation.

Meanwhile, selectivity, measured by etch rate, is a key performance index for etching. The criterion is the etch rate of the target layer compared to the etch rate of the layer that always plays a role in masking (PR film, oxide film, nitride film, etc.). This means that the higher the selectivity is, the faster the target layer is etched. The higher level of miniaturization requires a higher selectivity so that fine patterns can be properly realized. The selectivity of cationic etching is low since the direction is straight, but the selectivity of radical etching is high, resulting in the increased selectivity of RIE.

5. Etching Process

Figure 5. Etching Process

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First, a wafer is placed in a furnace of the oxidation process where the temperature is kept between 800 to 1,000 degrees Celsius, and then a silicon dioxide (SiO2) film with high insulating properties is formed on the wafer surface through a dry method. Then, it is moved to the deposition process to make a silicon layer or a conductive layer on the oxide film through the CVD/PVD process. If it is a silicon layer, impurities are diffused when necessary to increase conductivity. During diffusion, multiple impurities are often added repeatedly.
Now, the insulating layer and poly layer should be combined for etching. First, the photo resist (PR) is applied. Then, a mask is placed on the PR film and wet exposure is performed using an immersion method to engrave the desired pattern on the PR film (This is not visible to the naked eye). When development is performed to reveal the outline of the pattern, the PR of the photosensitive area is removed. Afterwards, the wafer that went through the photo process is transferred to the etching process to perform dry etching.

Dry etching is mainly performed in the RIE method, and it is repeatedly carried out by changing the source gas for each film. Both dry and wet etching are used to increase the A/R of etching Also, the polymer accumulated in the bottom of the holes (gaps formed by etching) is removed through periodic cleaning. What’s important is that all variables such as material, source, time, form, and order should be organically adjusted to allow the cleaning solution or plasma sources to move downwards to the bottom of the trench. Even a small change in one variable prompts recalculation of other variables, which should be repeated until the goal is met.

Recently, layers such as ALD are getting thinner and the material is getting harder. Accordingly, the etching technology is developing toward using low temperature and low pressure. The purpose of the etching is to control the CD, which makes fine patterns and ensure that there are no problems due to the action of etching, especially under-etching and the issue related to removal of residues. The most important things you should know in the two articles about etching are the purpose of etching, the obstacles to achieving that purpose, and the performance indices used to overcome those obstacles.

The post Etching, Process to Complete Semiconductor Patterning – 2 first appeared on SK hynix Newsroom.

1. Trend of Technological Development of Deposition and Etching

Figure 1. Trend of technological development of deposition and etching

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The process of forming a layer on a wafer is called deposition (CVD, ALD, and PVD) and the process of drawing a circuit pattern on the layer formed is called exposure. Etching is a process of carving the patterns on the wafers following the deposition and exposure processes. Since the photo process is like drawing a rough sketch, what really brings an apparent change to the wafers are deposition and etching processes.

There have been significant developments in both etching and deposition technologies since the birth of semiconductors. The most remarkable innovation in deposition technology was moving to a stacking method from a trench method in accordance with greater capacity of devices from 4 Megabit (Mb) DRAM from 1Mb in early 1990s. A pivotal moment for the etching technology was in early 2010s when 3D NAND flash cells were stacked in more than 24 layers. With the number of layers having increased to 128, 256, and 512 afterwards, etching has become one of the most technically difficult processes.

2. Changes of Etching Method

Figure 2. Development of etching method along with miniaturization (2D)

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The etching process has developed in accordance with the miniaturization progress of 2D (planar structure) semiconductors and the development of the stacking technology of 3D (spatial structure) semiconductors. In the 1970s, when 2D semiconductors were the mainstream, the circuit CD was rapidly decreasing from 100 micrometers (㎛) to 10 ㎛, or even lower. During this time, most of the line-up of the key process technologies of semiconductor manufacturing was finalized, while the transition of the etching technology from wet etching to dry etching was complete. For layer-cutting technology, chemical wet method, a relatively easy technique, was the first to be applied. As meeting the requirements for the 5 ㎛ of CD was difficult with the chemical wet method from early 1970s, a dry method using plasma was developed. Today, the dry method accounts for most of the etching process, while wet etching technique was later adopted and developed for the cleaning process.

3. Strengths and Weaknesses of Wet Etching and Dry Etching

Figure 3. Strengths and weaknesses of wet etching and dry etching

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With usage of a liquid, wet etching is faster, removing a greater depth per minute, but doesn’t result in a straight square-like structure. It etches all directions evenly. This leads to a loss in the lateral direction, which should be avoided for miniaturization of CD. On the contrary, dry etching allows cutting in a certain direction, making realization of the ultra-fine profile of the intended nanometer (nm) level possible.

Also, wet etching results in pollution since the used liquid should be discarded after the completion of the process. In contrast, dry etching uses a device called a scrubber in the middle of the discharge line to neutralize the exhaust gas before discharging into the air, resulting in less impact on the environment.

Meanwhile, since multiple layers are complicatedly intertwined on a wafer, it is difficult to target a certain layer (film) during etching. Wet etching is an easier option when targeting a certain film as it uses chemical reaction. It’s not easy to apply the dry method for selective etching as it’s a combination of physical and chemical techniques.

4. Etching Process Flow and Related Issues

Figure 4. Etching-related process flow

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The flow of the process starting from forming a film, applying PR on it and going through various steps like exposure, development, etching, ashing, cleaning, inspection and ion implantation is to create three TR terminals, the core process for semiconductor manufacturing. If the process of cutting the PR during the development step doesn’t go well, the remaining PR hinders etching. If a targeted layer is not sufficiently etched during the etching process, ion cannot be implanted as planned as impurity particles block. The same applies if the polymer residue remaining after dry etching is not thoroughly cleaned. If the amount of plasma ion gas is too large or a film is over-etched, due to a failure in time control, physical damage is caused on the lower film.

For this reason, it is crucial to find a precise end of point (EOP) in dry etching. It’s also important to thoroughly check the etching condition as well as the ashing and the cleaning process. A wafer could be rejected if it’s unevenly etched and under-etching is more fatal than over-etching.

Since the etching process involves complicated steps, I intend to divide the coverage into two parts. In this part, we’ve gone through the overall history and the direction of the etching technology development. We’ll look into more details of the relation between plasma and etching, RIE, one of the etching methods, the Aspect Ratio and the speed of etching in the next part.

The post Etching, Process to Complete Semiconductor Patterning – 1 first appeared on SK hynix Newsroom.