AI and high-performance computing (HPC) are evolving at an unprecedented pace, pushing traditional memory technologies such as DRAM and NAND flash to their limits. To meet the growing demands of the AI era, the industry is exploring emerging memory technologies which go beyond traditional memory.

Among these new memory technologies, storage-class memory¹ (SCM) has emerged as a key development as it can bridge the performance gap between DRAM and NAND flash. Recognizing the potential of SCM, SK hynix has developed selector-only memory² (SOM), a groundbreaking innovation that redefines SCM and strengthens the company’s AI memory portfolio.

¹Storage-class memory: A class of emerging non-volatile memory technologies that combines the speed of DRAM with the persistent storage capabilities of NAND flash. It bridges the gap between DRAM and NAND flash in terms of performance, cost, and storage capacity.
²Selector-only memory (SOM): A cross-point memory device featuring a chalcogenide-based film which can perform both selector and memory functions.

This final episode of  Rulebreakers’ Revolutions  explores the journey behind SOM’s development, the key role of SK hynix’s rigorous R&D approach, and the implications for the future of AI and HPC.

The Mission: Going Beyond Traditional Memory With Next-Gen SCM

The AI era has sparked a data explosion. AI systems, from large language models³ (LLMs) to multimodal AI⁴, require high-performance memory to rapidly access and process this vast amount of data and perform complex computations. This next-generation performance must be balanced with affordability and energy-efficiency, placing further pressure on memory technologies.

³Large language model (LLM): Advanced AI systems trained on vast amounts of text data to understand and generate human-like text based on the context they are given.
⁴Multimodal AI: Machine learning models capable of processing and integrate different types of data, including text, audio, and video.

To meet these increasing demands, HPC systems are transitioning from traditional CPU-centric models to memory-centric architectures. By supporting data processing directly within memory, these memory-centric systems can minimize data movement to ultimately improve system performance and efficiency.

Amid this shift, the industry is exploring new memory technologies which can surpass the capabilities of traditional memory. Among them, SCM has emerged as a promising solution by bridging the performance gap between DRAM and NAND flash. As a non-volatile memory, SCM combines the speed and cost-efficiency of DRAM with the high capacity of NAND flash. Additionally, the advent of CXL^®5 technology has enabled seamless connections between memory and devices such as CPUs, GPUs, and accelerators, creating new opportunities for SCM adoption in advanced computing.

⁵Compute Express Link^®(CXL^®): A next-generation interface that connects the CPU, GPU, memory, and other components to efficiently enhance the performance of high-performance computing systems.

Recognizing the capabilities of the technology, SK hynix took on the challenge of developing a next-generation SCM product—SOM—which could revolutionize the industry.

SK hynix’s SOM goes beyond traditional memory, breaking the barriers to next-generation memory

Beyond 3DXP: Rigorous R&D and Collaboration Unlock SOM

Before developing SOM, SK hynix had made great progress with an alternative SCM technology—3D XPoint (3DXP). Developed in the mid-2010s, 3DXP was a non-volatile storage technology that used phase-change memory (PCM)⁶ to store data through changes in material resistance states. It employed a transistor-less, cross-point architecture⁷ featuring selectors⁸ and memory cells placed at the intersection of perpendicular wires. By stacking 3DXP cells in a three-dimensional architecture without transistors, the product offered high memory density.

⁶Phase-change memory (PCM): A technology which enables non-volatile electrical data storage at the nanometer scale. PCM memory switching involves heating materials so they switch between amorphous and crystalline states, which correspond to the binary digits 0 and 1, respectively.
⁷Cross-point architecture: A memory architecture where data is stored at the intersection, or “cross-point”, of two or more lines in a grid-like structure.
⁸Selector: A device in a memory array that regulates the flow of current to and from a memory cell. This enables precise access to a specific cell while blocking unwanted paths for more accurate read and write operations.

Despite the potential of 3DXP, SK hynix identified challenges regarding the product’s scalability beyond 20 nm process technology. As a result, the company switched its attention to an alternative next-generation SCM product.

The company set about developing SOM, a groundbreaking cross-point memory device that uses a single chalcogenide⁹ -based film, known as dual-functional material (DFM), to perform both selector and memory functions. Compared to 3DXP, SOM eliminates the need for the separate selector and PCM setup. Instead, selectors in SOM are deployed without standalone memory cells to improve selector functionality. Moreover, SOM utilizes an optimized cross-point array with lower cell stack aspect ratios¹⁰ for better scalability and higher memory density.

⁹Chalcogenide: A chemical compound consisting of at least one chalcogen anion, such as sulfur, and an electropositive element, such as metal.
¹⁰Aspect ratio: Height-to-width ratio of memory cells.

One of the biggest changes from 3DXP was the inclusion of DFM in place of phase-change material. As a result of this switch, SOM offers advanced specifications. Firstly, the write speed is significantly improved as DFM, unlike PCM, does not require time to perform phase changes. While PCM required a high write current for joule heating during phase transitions, the use of DFM significantly reduced the necessary write current. In addition, DFM offers increased stability when operating at high temperatures, reducing thermal disturbance¹¹. DFM’s improved heat resistance also ensures it offers enhanced cyclic endurance compared to PCM, boosting overall durability.

¹¹Thermal Disturbance: A phenomenon where heat generated while programming one memory cell unintentionally affects the state of neighboring cells due to heat diffusion, potentially disrupting their data integrity.

SOM replaces the phase-change material used in 3DXP with DFM

The successful development of SOM would not have been possible without SK hynix’s rigorous approach to R&D and smooth internal collaboration. For example, the company discovered DFM during research on chalcogenide-based selector and memory materials. By applying a new bipolar operation instead of the conventional unipolar operation, the team found it could achieve both selector and memory characteristics simultaneously.

The company’s R&D approach also enabled a significant reduction in SOM’s power consumption compared to pre-development expectations. When conventional optimization approaches proved insufficient, this prompted a radical reexamination of materials, design, and operational algorithms. In response, various research teams came together to collaborate on the project and develop new approaches. They tested the application of new materials and operational techniques through simulations, addressing any potential issues. This meticulous process cut power consumption by approximately one-third from initial predictions, a crucial advancement in the development of SOM.

Unveiling the World’s Smallest SOM

SK hynix has successfully developed the world’s smallest SOM, the first fully integrated¹² 16nm half-pitch¹³ SOM. This revolutionary achievement in the SCM field was presented at the prestigious 2024 IEEE Symposium on VLSI Technology and Circuits (2024 VLSI Symposium).

¹²Fully integrated: Complete integration of circuits and manufacturing processes at the cell array level, unlike basic single-cell prototypes in academic research.
¹³Half-pitch: Half of the minimum center-to-center distance between interconnect lines in a semiconductor.

Compared to 3DXP, SOM offers a reduction in write speed from 500 nanoseconds (ns) to 30 ns and write current, which dropped from 100 microamps (µA) to 20 µA. In addition, cyclic endurance increased from 10 million to over 100 million cycles, highlighting SOM’s increased durability. SOM was also shown to have advanced persistency, the ability to retain data under extreme conditions, as tests proved it could retain data for over 10 years at 125°C.

SOM offers outstanding capabilities from rapid write speed to advanced persistency

Significantly, the 16nm SOM is the smallest, most scalable and high-performing cross-point memory solution on the market. As the AI landscape continues its evolution, the successful development of SOM strengthens SK hynix’s AI memory leadership, complementing products such as HBM, AiMX, and CXL Memory Module (CMM)-DDR5.

Looking forward, the research behind SOM will contribute to broader advancements in next-generation memory technology. Its impact extends to the growing field of heterogeneous integration, enabling innovative system integration approaches that cater to AI data centers and diverse AI solution providers. As computing architectures shift towards memory-centric computing, SOM’s technological breakthroughs will play a crucial role in shaping the future of AI and HPC.

Rulebreaker Interview: Myoungsub Kim, Global Revolutionary Technology Center (RTC)

To find out more about the company’s innovative approach to SOM development, the SK hynix Newsroom spoke with Myoungsub Kim of the Global Revolutionary Technology Center (RTC), which conducts R&D of next-generation semiconductors. Kim discusses the major challenges faced when developing SOM as well as the rulebreaking mindset adopted by employees.

<Other articles from this series>

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

[Rulebreakers’ Revolutions] How SK hynix’s Server DRAM Validation Process Succeeds in a Diverse Server CPU Market

[Rulebreakers’ Revolutions] Flexible & Collaborative eSSD Virtualization Development for Today’s Data Centers

[Rulebreakers’ Revolutions] How SK hynix’s Design Innovations Pushed GDDR7 to New Limits of Speed

[Rulebreakers’ Revolutions] How CXL Tech Expands Data Center Memory Scaling Boundaries in the AI Era

The post [Rulebreakers’ Revolutions] How SK hynix’s SOM Paves the Way for Next-Gen Memory in the AI Era first appeared on SK hynix Newsroom.

¹InGaZnO: A semiconducting material consisting of indium (In), gallium (Ga), zinc (Zn), and oxygen (O).
²Thin-film transistor (TFT): A type of MOSFET fabricated through thin-film deposition traditionally used in liquid crystal displays (LCDs).
³Thermal budget: The total amount of thermal energy or heat that can be dissipated or allowed within a device without exceeding its specified temperature limits.

In light of this, SK hynix’s Revolutionary Technology Center (RTC) conducted research on crystalline IGZO (c-IGZO) TFTs and compared their characteristics with a-IGZO TFTs. Presented at the 2023 Very Large-Scale Integration (VLSI) Symposium, the study aimed to demonstrate that c-IGZO TFTs can be more thermally stable than a-IGZO under hydrogen-rich processes.

Demonstrating the Thermal Stability & Hydrogen Process Resistance of c-IGZO

Figure 1. (a) The various process steps involving hydrogen at 550°C after IGZO deposition. (b) Transmission electron microscopy (TEM) images of a-IGZO and (c) c-IGZO before and after subsequent deposition processes and electron energy loss spectroscopy (EELS) images after processing.

Figure 2. (a) The transfer characteristics of a-IGZO (A’) and c-IGZO TFTs (A-D), which have incrementally increasing amounts of gallium from A to D, at a drain voltage (V_ds) of 1V (W/L=0.8/0.1 micrometers [μm]). (b) A comparison of the on-current (drain current [I_ds] at gate voltage [V_gs]-threshold voltage [V_th]=3V) with V_th performance for various IGZO conditions.

As shown in Figures 1 (b) and (c), agglomeration⁴ was observed in a-IGZO following several high thermal hydrogen-rich deposition processes, while c-IGZO remained stable without structural changes. This suggests that c-IGZO is significantly more resistant to hydrogen at high temperatures than a-IGZO and enables additional oxide thickness (T_ox) scaling. Meanwhile, Figure 2 (b) shows that the threshold voltage (V_th) can be controlled by adjusting the composition of c-IGZO (A to D). When c-IGZO demonstrated a similar V_th to a-IGZO, the on-current (I_on) was 1.8 times higher in c-IGZO (C) than a-IGZO (A’).

⁴Agglomeration: The process of particles or granules sticking together to form larger clusters or agglomerates.

Figure 3. An off-current at 25°C of c-IGZO (C) TFT with a channel length of 70 nanometers (nm) extracted from an Arrhenius plot

Figure 4. The transfer characteristics of a-IGZO (T_ox=100Å) and optimized c-IGZO TFT (T_ox= 50Å). (V_ds = 1V)

Figure 5. The optimized c-IGZO (T_ox =50Å) TFT after positive bias temperature stress (PBTS) testing for 1,000 seconds (s).

Figure 3 shows that extremely low I_off of 1.82×10⁻¹⁸ A/micrometers (μm) was demonstrated in the c-IGZO TFT with a channel length⁵ (L_g) of 70 nanometers (nm). This suggests that c-IGZO can be a feasible material for DRAM cells as it offers a long data retention time.

The researchers also found that, through composition control and T_ox scaling, the subthreshold swing⁶ and I_on of the optimized c-IGZO showed significant improvement (Figure 4). Furthermore, Figure 5 shows that despite the relatively thin T_ox of 50Å, the optimized c-IGZO device demonstrated similar V_th shift (ΔV_th) as a-IGZO (+19 millivolts [mV]) after the positive bias temperature stress⁷ (PBTS) test. This indicates that c-IGZO has better V_th stability than a-IGZO.

⁵Channel length: A critical dimension of a MOSFET which represents the length of the semiconductor channel between the source and drain terminals.
⁶Subthreshold swing: The amount of change in the gate voltage required to change the drain current by a factor of 10.
⁷Positive bias temperature stress (PBTS): A reliability test for a semiconductor device which involves subjecting the device to elevated temperatures while applying a positive bias voltage to the gate terminal.

C-IGZO: The Future of Next-Gen Memory Channel Materials

The researchers found that c-IGZO has better thermal stability and is more immune to hydrogen processes than a-IGZO. Due to these characteristics, c-IGZO can be an excellent candidate for new channel materials in future memory devices with high thermal budgets.

For more information regarding RTC’s research, please visit the center’s research website (https://research.skhynix.com). The RTC operates the site to share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.

The post Crystalline IGZO Transistors With High Thermal Stability Show Promise for Next-Gen Memory Channels first appeared on SK hynix Newsroom.

The Revolutionary Technology Center (RTC), established under SK hynix’s Future Technology Research Institute, conducts global research on the memory technologies of tomorrow. In order for RTC to go beyond the technical boundaries of semiconductor memory, the center actively communicates and collaborates with various international research organizations. To find out more, the SK hynix Newsroom met with three RTC members who are expanding the center’s research by working with two major organizations—the Interuniversity Microelectronics Center (IMEC) in Belgium and the U.S.-based Semiconductor Research Corporation (SRC) . In the interview, RTC Technical Leaders (TL) Jaegil Lee, Yulim Son, and Wontae Koo discuss the center’s global R&D culture and research vision for the future.

¹Interuniversity Microelectronics Center (IMEC): Established in 1984, IMEC is a non-profit semiconductor research organization based in Belgium. It operates as a joint industry-academia-research technology development consortium and includes major E.U. universities and leading global semiconductor companies.
²Semiconductor Research Corporation (SRC): A world-class technical research cooperative organization founded in 1982 by Erich Bloch of IBM. It is a partner of the Semiconductor Industry Association (SIA) and operates a variety of programs to meet the technology and talent development needs of the semiconductor industry.

▲ (From left) RTC Future Memory Research team members Wontae Koo, Yulim Son, and Jaegil Lee

Realizing Synergies With IMEC

Jaegil Lee recently returned to RTC at its Icheon campus in South Korea following his secondment to IMEC. IMEC, one of the top three semiconductor research centers in Europe, focuses on researching advanced technologies which are difficult for businesses to implement. In particular, it functions as a test bed to determine the potential of next-generation technologies at an early stage, and conducts research collaborations and exchanges with leading global semiconductor companies. SK hynix has been an IMEC member since 2007 and has consistently strengthened its partnership with the center over the years to research future technologies.

▲ RTC’s Jaegil Lee speaks about his two-year secondment at IMEC

“When the decision was made to send me to IMEC, I was most looking forward to experiencing in person the advanced technologies which the center is researching and working on new projects together,” Lee said.

During his two years at IMEC, he achieved several notable feats including the discovery and valuation of new devices. He also initiated several projects and conducted joint research.

In his role as an on-site manager of the research program between RTC and IMEC, Lee worked with IMEC researchers as well as managers and engineers from other member companies. “I was impressed by the fact that IMEC is not only a research center, but also a place to exchange technologies and opinions across the semiconductor ecosystem,” he said. “Interacting with researchers from various industries, regardless of their affiliation or nationality, expanded my thinking and opened my eyes to the strengths and synergies of collaborative research.”

▲ IMEC’s Technical Account Director Alessio Spessot and RTC’s Jaegil Lee discuss IMEC’s work

IMEC’s Technical Account Director Alessio Spessot, who is in charge of managing and supporting fieldwork for dispatched researchers at the center, emphasized the importance of collaboration in the industry.

“Semiconductor research can only be completed when the industry ecosystem moves together and helps each other,” he said. “IMEC conducts collaborative research to determine the R&D direction which helps to develop a good overview of research tasks needed in the industry and form a relevant roadmap.

“SK hynix’s dispatched researchers, executives and employees of related departments at the company headquarters are providing feedback on the progress and assisting with research.”

Conducting Global Open Research With SRC

Funded by the U.S. government, related groups and over 30 global semiconductor companies, SRC creates and supports industry-academia research programs and shares the results. Currently, about 2,400 research professors and 14,000 students from 250 universities in 25 countries are taking part in SRC activities. As an SRC member, SK hynix has participated in various related research programs. These programs have enhanced the RTC’s research capabilities and cooperation with partner organizations, and helped to foster industry manpower.

▲ The RTC researchers discuss the center’s global research collaborations

As SRC is one of the main partners of the RTC’s open research platform³, joint research projects are conducted on a regular basis. To facilitate these projects, RTC’s Wontae Koo and Yulim Son carry out various related tasks.

³Open research platform (ORP): A platform that conducts research that is widely accessible and develops an open ecosystem by encouraging research collaborations.

Koo monitors research on future technologies by overseas research groups participating in the SRC program and explores new technologies. Through this, he secures a pool of technologies which can be used in the company’s next-generation memory products and conducts research by thoroughly analyzing and verifying technologies with high potential. Meanwhile, Son is in charge of communicating the status of joint research projects to RTC to ensure they are useful to the center, and disseminates the results to related departments within SK hynix.

▲ RTC’s Wontae Koo and Yulim Son talk about their work with SRC

This strong communication led to a major achievement for Koo. He exchanged feedback with overseas research groups participating in the SRC program and was recognized for his contribution by being listed as a co-author on a paper. “While analyzing SRC research materials that would be helpful to RTC, I discovered a project which could proceed to simulation by combining our data,” he said. “Through communication with professors and researchers, we developed the content in a beneficial direction which led to me being listed as a co-author in an international journal.”

Koo’s achievement highlights how global SRC members participate in project selection and frequently share research progress. Furthermore, there is active communication between member companies and researchers.

▲ An SRC technology research workshop held at Icheon campus on November 9^th, 2023

In addition to industry-academia research projects, RTC is continuing various exchanges with SRC. On November 9^th, 2023, RTC held a technology research workshop with SRC faculty. During the event, participants shared research and technology insights on topics such as future devices and technologies, processes and materials, and package and system design. The sessions were also broadcast online to boost members’ interest in future technology research.

Son, who helped plan and operate the workshop, said: “SRC is the optimal platform for those who are looking for future technology research trends and new learning opportunities.

A Global Culture for Research Without Borders

▲ The interviewees share their thoughts on the benefits of the RTC’s global outlook

As semiconductor technology advances, the issues that must be solved to develop next-generation solutions are becoming increasingly complex. In order to effectively respond to the rapidly changing business environment and trends and lead future technology research, RTC aims to expand its research partnerships rather than rely solely on its own capabilities.

“Collaborations with global research institutes and diverse experts are an effective way to reduce research times and costs, and accelerate the realization of future technologies,” said Son.

As academia and industry have different perspectives on technology, collaboration is a means for each sector to complement each other. Koo said: “While those in academia focus on the technology itself and study its principles and feasibility, researchers in the industry consider the product applicability and marketability of the technology in many ways.

“Communication through such collaboration is mutually beneficial. It is an opportunity to understand and expand the semiconductor ecosystem,” Koo added. “RTC is trying to analyze possibilities with an open mind while maintaining a balanced view on new technologies by accepting the perspectives of both academia and industry.”

Lee emphasized that RTC already operates with a global culture as it conducts open research on advanced technologies which crosses borders. “I think the current RTC research culture is open and horizontal so it is no different from IMEC,” he said. “This is because we have a global mindset which allows for the free expression of opinions and provides sufficient support to develop small ideas. Based on this, RTC will be able to predict the markets of tomorrow and develop appropriate new technologies.”

Researching the Technologies of Tomorrow

As noted by the interviewees, RTC recognizes the importance of global research collaborations in the semiconductor industry to share different opinions and technologies and propel the sector forward. Looking ahead, RTC will further strengthen its partnerships with international research organizations to ensure it continues to develop future memory solutions which push technological limits.

RTC operates a research website (https://research.skhynix.com) to share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.

The post RTC Members Reveal How Global Research Collaborations Unlock Tomorrow’s Memory Solutions first appeared on SK hynix Newsroom.

In 2022, researchers at SK hynix’s Revolutionary Technology Center (RTC) revealed they had demonstrated 3D Fe-NAND triple-level-cell² (TLC) operation using the ferroelectric HfO₂³. This article will focus on the RTC’s latest research presented at the 2023 Very Large-Scale Integration (VLSI) Symposium, which showed 3D Fe-NAND quad-level cell⁴ (QLC) operation for the first time using the 3D CTN NAND test vehicle⁵.

¹Ferroelectric (FE): A material which exhibits spontaneous electric polarization without an external electrical field that can be reversed in direction by the application of an appropriate electric field.
²Triple-level cell (TLC): A form of NAND flash memory that can store up to 3 bits of data per memory cell.
³Hafnium Oxide (HfO₂): A mature high-k dielectric applied to semiconductor materials due to its high dielectric constant, thermodynamic stability, and the simplicity with which it can be deposited.
⁴Quad-level cell (QLC): A form of NAND flash memory that can store up to 4 bits of data per memory cell.
⁵Test vehicle: A circuit or IC designed for the purpose of evaluating one or many device characteristics.

Finding the Ideal Cell Structure to Increase the PE Window

For 3D Fe-NAND to realize TLC and QLC operation, it required further expansion of the program/erase (PE) window⁶. The latest RTC research proposed novel 3D Fe-NAND cell structures that can enlarge the PE window up to 10.54 V through cell stack optimization, thereby demonstrating the feasibility of QLC operation.

⁶Program/erase window (PE window): The process window of erasing and writing a cell. The more P/E cycles that the NAND technology can sustain, the better the endurance of the device.

Figure 1. Table showing key characteristics of four cell stack structures (S1–S4)

Figure 2. Graphs comparing the (a) erase and (b) program performances of S1–S4

Figure 1 summarizes the four types of cell structures (S1–S4) evaluated in this study and compares the electrical characteristics including the standard PE window, the post 3k cycle PE window, and the channel to gate leakage current. Figure 2(a) and (b) show the transfer characteristics of the four cell structures as the researchers erased and programmed the cells using the conventional ISPE⁷ and ISPP⁸ methods. In particular, S4 achieved the enlarged P/E window of 10.54 V by reducing the leakage current and optimizing the cell structures of the ferroelectric stack and the top interlayer.

⁷Incremental Step Pulse Erase (ISPE): A memory programming method in which a memory element is programmed to a specific state or set to an erase state using small, incremental voltage steps or pulses.
⁸Incremental Step Pulse Programming (ISPP): A memory programming method in which a series of programming pulses of increasing magnitude are applied to select memory cells to gradually raise their threshold voltage.

Figure 3. Line graphs for S4 showing its (a) TLC threshold voltage (V_th) distribution (b) QLC V_th distribution and (c) post 3k cycle V_th distribution

Both TLC and QLC operations were performed on S4. Figure 3(a) shows TLC verification results for S4 with the minimum gap margin of 0.45 V between two adjacent threshold voltage (V_th) states. This represents a significant improvement from the RTC’s previous data, which showed a minimum gap margin of 0.11 V. Moreover, with the expanded PE window, Figure 3(b) shows S4’s QLC operation is demonstrated with the minimum gap margin of 0.24 V. In Figure 3(c), QLC Vth distribution after 3k cycling stress is shown with the reduced minimum gap margin of 0.14V. The QLC operation after the 3k cycle is verified not only by expanding the PE window, but also by improving endurance properties as a result of cell stack engineering.

3D Fe-NAND Opens the Door to a New Era

To overcome the limitations of conventional 3D CTN NAND, the researchers successfully fabricated the HfO₂-based 3D Fe-NAND. The new NAND research shows that optimizing the cell stack leads to an expansion of the PE window, while the QLC operation was also demonstrated which suggests that 3D Fe-NAND is a promising potential solution in the post-3D NAND era.

For more information regarding RTC’s research, please visit the center’s research website (https://research.skhynix.com). The RTC operates the site to share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.

The post 3D Fe-NAND to Surpass 3D CTN Memory Following Cell Stacking Breakthrough first appeared on SK hynix Newsroom.

¹Memory hierarchy: Memory can be divided into a hierarchy based on speed as well as use. A typical memory structure includes cloud, flash, DRAM, cache and register memories.
²Compute Express Link (CXL): PCIe-based next-generation interconnect protocol on which high-performance computing systems are based.
³3D XPoint (3DXP): Developed by Intel and Micron, 3DXP is a non-volatile phase change technology that serves as both memory and storage. Cell arrays consist of simple stackable crossbar structures for multiple layers.

This article will focus on research into developing a four-deck 3DXP solution which was presented at the 2023 Very Large-Scale Integration (VLSI) Symposium, one of the world’s top three semiconductor conferences. It also considers the scaling limitations of 3DXP and the potential for selector-only memory (SOM) to be the future of storage class memory (SCM).

Advancing 3DXP Through Novel Integration Schemes

Figure 1. (Left) Cross section transmission electron microscopy (TEM) of two-deck and four-deck cell arrays with a copper multi-layer and peri under cell (right) Floorplan of a 20 nm four-deck chip with a capacity of 256 Gb

SK hynix has made significant progress in its development of 3DXP memory solutions over the past few years. At the 2018 International Electron Devices Meeting (IEDM), SK hynix shared the results of its two-deck 64 Mb test chip operation with 2z⁴ nanometer (nm) technology, and then successfully demonstrated a 128 Gb chip in 2019. More recently, the company demonstrated progress on a four-deck 256 Gb chip with 20 nm technology at the 2023 VLSI.

⁴2z: The third generation of 20 nm process technology in which “z” refers to the lower third number range of the 20 nm class, which covers 20 nm-29 nm. The letters “x”, “y” and “z” are used to refer to the upper, middle, and lower thirds, respectively, of the relevant process technology class such as 10 nm, 20 nm etc.

Figure 2. (Left) Voltage distribution of each deck after set and reset operations (right) Basic die information, including structure and operation properties, of the four-deck chip

To create this latest solution, SK hynix developed novel integration schemes including new self-align etching, cleaning, chemical mechanical polishing (CMP), and interlayer dielectric (ILD) deposition. A low-resistance conductor material was also developed for the interconnection scheme to ensure a sufficient flow of write current while minimizing spike current. In addition, a large read window margin⁵ and a tight voltage distribution of the 1 Gb array for each deck were achieved by carefully controlling the 20 nm pillar patterning process, material design, and appropriate write/read operation.

⁴Read window margin (RWM): The threshold voltage (Vt) interval (ΔVt) at distribution tails. When using a chalcogenide material such as PCM, it has a Vt distribution similar to DRAM or NAND. The Vt interval between the Vt distribution of 0 and 1 is regarded as the sensing margin, or the read window margin.

Overcoming Limitations of 3DXP With SOM

Figure 3. Scaling challenges of 3DXP presented in three graphs: (left) Aspect ratio (center) Set program margin (right) Thermal disturbance

Although the researchers successfully demonstrated a four-deck 256 Gb device, they discovered issues when assessing the scalability of 3DXP beyond 20 nm technology. First, the structure of 3DXP, which consists of phase-change memory (PCM)⁶ and an ovonic threshold switch (OTS)⁷, will have a much higher aspect ratio⁸ as the technology is scaled down and this will lead to complex progress integration. Second, 3DXP will have a smaller write program margin between set and reset operations as the technology node shrinks. Third, the scaling limit by thermal disturbance is expected to occur at technology nodes beyond 1y nm without the elusive thermal conductivity of inter-layer dielectric.

⁶Phase-change memory (PCM): A technology which enables nonvolatile electrical data storage at the nanometer scale. A PCM device consists of a small active volume of phase-change material placed between two electrodes. A common PCM material is germanium-antimony-tellurium (GeSbTe).
⁷Ovonic threshold switch (OTS): A two-terminal symmetrical voltage sensitive switching device which, after being brought from the highly resistive state to the conducting state, returns to the highly resistive state when the current falls below a holding current value.
⁸Aspect ratio (AR): The ratio of height to width. A high aspect ratio means that the structure is narrow but tall.

Figure 4. Memory requirement relationship between performance, which indicates bandwidth, and cost

As a result of these limitations, SK hynix is preparing SOM as an alternative solution for the next generation of storage class memory. SOM is composed of only two electrodes and a single dual-functional material which can operate as both the memory and selector. Compared to 3DXP, SOM offers lower write latency and cell power consumption as it eliminates 3DXP’s long crystallization time for the set operation and high reset current. Therefore, SOM is set to be a leading solution for next-generation applications with scaling longevity beyond 1z nm technology.

For more information regarding RTC’s research, please visit the center’s research website (https://research.skhynix.com). The RTC operates the site to share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.

The post Beyond 20nm 3DXP: Why Selector-Only Memory is the Future for Ultra-Fine Processes first appeared on SK hynix Newsroom.

“Research in future technologies is a battle of ideas, and a flexible research culture is key to promoting creativity. A habit of collaborating is also crucial as innovation does not happen with one person.”

The Revolutionary Technology Center (RTC) is SK hynix’s future technology research organization that has already grown into a notable institution despite only being established in 2021. Based on the model of an open research platform (ORP)¹, the organization is actively engaged in research collaborations and academic activities.

¹Open research platform (ORP): A platform that conducts research that is widely accessible and develops an open ecosystem by encouraging research collaborations.

It would not be an understatement to say that RTC’s unique organizational culture is responsible for its rapid growth. A horizontal work culture, systematic research collaborations, and an agile work process have made positive outcomes. To find out more about the organization’s secrets to success, the SK hynix Newsroom interviewed three RTC members to discuss the center’s unique research methods and distinct work culture.

RTC Plants Seeds of Future Technologies

There have been countless companies that have faded into obscurity because they could not respond quickly enough to digital transformations or a rapidly changing market. The semiconductor sector is no exception as it no longer relies on once core concepts such as Moore’s Law² and the Von Neumann³ architecture. As the shrinkage of devices has now nearly reached its limit, it has become difficult to increase memory speed and capacity using only conventional processes. Meanwhile, it has also become impossible to compute large-scale data using just the Von Neumann architecture, which splits semiconductors into system and memory. As a result, innovation has become important in all aspects of semiconductor development, and research on future technologies has become a matter of survival in this rapidly changing market.

²Moore’s Law: Devised by Intel Co-Founder Gordon Moore, Moore’s Law states that the number of transistors on a chip doubles every one to two years.
³Von Neumann architecture: A program-embedded computer structure typically featuring three levels consisting of the main memory unit, a central processing unit, and an input/output unit. Most computers today follow this basic structure, but its bottleneck limits the ability to design high-speed computers.

Accordingly, RTC’s goals include maintaining SK hynix’s competitiveness in the global market through advancements in DRAM and NAND flash and researching new types of memory. The center also aims to expand semiconductor technologies that can be compatible with next-generation solutions like high-performance computing.

According to Jungwook Woo of the Revolutionary DRAM team, RTC is an organization that acts as a guide to navigate SK hynix’s path forward.

▲Jungwook Woo talks about the role of RTC and the importance of revolutionary semiconductors

“I think RTC shows the way for our workforce to march forward,” he said. “This means exploring future technologies and markets while conducting pilot studies on technologies that show potential in paving the way for future business items.”

In particular, the Future Memory Research team that Lee is a part of is looking even 30 years into the future. The team draws up a future roadmap ranging around 10 to 30 years and looks at all the technologies that may be involved in this timeframe. Lee explains that it is like finding a gemstone and polishing it into jewelry.

“You can think of it as planting seeds, just like the magic beans in Jack and the Beanstalk,” he said. “In short, RTC’s job is to plant the seeds of future technologies that will eventually blossom into fine objects such as jewelry.”

Communicating Without Barriers and Moving With Shrewdness

Imagination, creativity, and ideas are the cornerstones of RTC, as it sets the focus of its pilot studies on preparing for the future rather than staying in the present. Thus, the horizontal culture of the center stands out even within SK hynix which already had a company-wide horizontal culture. Lee thinks that imagination and ideas are fostered by such open communication in a welcoming environment.

▲ Woocheol Lee describes RTC’s unique culture of open communication

“It is common to communicate through online messages at RTC,” said Woocheol Lee of the Future Memory Research team. “We do not usually write long emails or follow overly formal procedures if they are deemed unnecessary. This more relaxed approach to communication also makes it easy to talk to executives. I remember the time RTC Vice President Myung-hee Na prepared a personalized presentation due to a question I had asked her.”

Another feature that exemplifies RTC’s culture is its creative research program. The center organizes events such as Patent Day and the Innovation Box Festival to encourage a culture of open research and communication.

Patent Day is a program aimed at responding to future technologies and securing patents. Each team researches several patents and works together to develop a new one. Once the teams have developed their ideas, the center hosts Patent Day. Meanwhile, the biannual Innovation Box Festival promotes the development of future technologies. Members set aside some of their work time to transform their concepts for new technologies into concrete proposals. The selected entries become the subject of pilot studies, and the findings from the research are then encouraged to be used for patent submission or academic work.

These two programs have been praised by RTC members for encouraging creativity. “I often have random ideas floating in my head, and the center allows me to pursue these ideas in real life,” said Jaehyuk Park from the SOM Cell team.

RTC members have also stated that forming diverse project teams has proved to be very helpful for research. But such collaboration and the aforementioned open communication and creative research methods are not the only pillars of RTC’s organizational culture. Agility is also cited as a key aspect of life at RTC and this approach has enabled the center to conduct its research efficiently.

Being agile at RTC can be exemplified when its experts from different teams promptly gather together to conduct pilot studies and then turn their attention to a different task after completing their preliminary research. Woo’s team was also reorganized as a reaction to shifts in technology trends. In order to anticipate the possibilities of various technologies alongside changes in the market environment, agile research and development are conducted while the direction of work is frequently reviewed. This allowed RTC to quickly move forward with the time-sensitive pilot study. Woo considers this agile mindset a major advantage for the organization.

“In the case of pilot studies, the success or failure of the project is determined in the early stages. So, setting KPIs for the whole year may make a company miss the opportune time to conduct research. RTC, on the other hand, makes swift reviews on issues for quick decision-making and sets the right direction for the course of its projects to maintain its agile mindset.”

More Patents and Conference Presentations Thanks to a Unique Organizational Culture

The center’s organizational culture has been grounded in the belief that good processes produce good results. Lee emphasizes that Patent Day provided in-depth discussions with team members that were a great help on his road to achieving goals.

“After joining the company in 2021, I came up with several patents and a few of them have been successfully filed,” Lee said. “I was able to achieve this milestone due to the environment here that encourages filing patents, sharing ideas, and seeking challenges even if we fail at times.”

As for Park, he recently completed a pilot study on an idea that was chosen at the Innovation Box Festival.

▲Jaehyuk Park describes his participation in the Innovation Box Festival and his accomplishments

“Our team came up with an idea that was selected at the Innovation Box Festival, so we were able to conduct a pilot study that was based on the idea,” Park recalled.

As these examples show, a lot of the research conducted at RTC is actively shared among its members. This is due to RTC’s goal of becoming a collaborative research organization that expands boundaries from its internal organization to external parties. Accordingly, a lot of Lee’s work includes collaborations with overseas research institutions.

▲(From left) Woocheol Lee, Jaehyuk Park, and Jungwook Woo discuss about participating in various research projects

“We are exploring future technologies with overseas research institutes such as the Semiconductor Research Corporation (SRC), Interuniversity Microelectronics Centre (IMEC), and Stanford University’s Stanford SystemX Alliance,” Lee said.

The active research and sharing that is taking place among members is also starting to pay off at the organizational level. The number of papers submitted to world-renowned conferences such as the IEEE International Electron Devices Meeting (IEDM) and IFIP/IEEE International Conference on Very Large Scale Integration (VLSI) is increasing every year. Lee thinks that these achievements are just the tip of the iceberg.

“We now want to collaborate openly on research that was previously only conducted internally,” Lee said. “As this is just the beginning for RTC, there will be further achievements down the road. If our quality collaborations and shared achievements continue, I think RTC will grow into an ORP where everyone researches together.”

An Organization Moving Into the Future With a Shared Vision

RTC has a number of initiatives to strengthen its internal communications including roundtable meetings, newsletters, and vision-sharing sessions. Many members point to these vision-sharing sessions that look at the current state of the organization and research trends as the secret to RTC’s strength. The sessions help members look objectively at where they are, suggest ways to improve, and keeps everyone on the same page.

▲(From left) Jaehyuk Park, Woocheol Lee, and Jungwook Woo talk about their approach to future semiconductor research

As for the three interviewees, they have different personal missions for the future. Woo wants to be “a scout that conducts pilot studies to propose the path for the main unit to move forward”, while Park holds the notion that “all innovations start with my work as they deal with cells, the foundation of semiconductors.” Meanwhile, Lee conducts his research with the mindset of “creating game-changing technologies that contribute not only to the company but to humanity itself.”

In the end, all three members are confident that RTC will lead the way in turning new ideas into reality and, consequently, contribute to changing the world.

The post Open Communication, Creative Research, and Agile Problem-Solving: The Keys to RTC’s Advances in Semiconductor Research first appeared on SK hynix Newsroom.

¹Capacitance: The ability of a component or circuit to collect and store energy in the form of an electrical charge.
²Dielectric (DE): Insulators that become polarized to support an electrostatic field when they are exposed to an electric field.
³Dielectric constant: A value representing the electrical dielectric properties of the dielectric. The higher the dielectric constant, the more charge the dielectric can accumulate.

To further the development of such materials, SK hynix’s Revolutionary Technology Center (RTC) conducted a study which fused ultra-thin ferroelectric⁴ (FE) and anti-ferroelectric⁵ (AFE) materials, respectively, with ultra-thin dielectric materials as shown in Figure 1. This article will summarize the process and results of the study, which were first announced at the IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2023.

⁴Ferroelectric (FE): A material which exhibits spontaneous electric polarization without an external electrical field that can be reversed in direction by the application of an appropriate electric field.
⁵Anti-ferroelectric (AFE): A material which exhibits ferroelectric polarization properties in external electric fields but does not have spontaneous polarization in the absence of external electric fields.

Figure 1. [Left] Schematic diagram and planar view of FE/DE and AFE/DE pillar-type DRAM capacitors with the same structure. [Right] Thin films of O-phase rich HZO FE double layers and T-phase rich HZO AFE double layers are applied to determine which is most effective.

To determine whether FE or AFE materials are more suitable for use as a DRAM cell capacitor, hafnium zirconium oxide⁶ (HZO)-based FE (O-phase⁷ HZO) and AFE materials (T-phase⁸ HZO), which are highly compatible with the CMOS process, were used to manufacture ultra-thin FE/DE and AFE/DE double layers.

⁶Hafnium-zirconium oxide (HZO): Oxide (HfZrO2) consisting of hafnium (Hf) and zirconium (Zr).
⁷Orthorhombic phase (O-phase): A crystal structure with three different axes at right angles. O-phase HZO shows ferroelectric properties.
⁸Tetragonal phase (T-phase): A crystal structure in which three axes are at right angles and two of them are the same. T-phase HZO shows electrical properties similar to anti-ferroelectricity.

For the study, the FE and AFE properties of the fabricated double layers were controlled. An analysis was conducted of the correlation between equivalent oxide thickness⁹ (EOT), a key characteristic of DRAM capacitors, and residual charge¹⁰ (Qrem), a core property of ferroelectrics.

⁹Equivalent oxide thickness (EOT): The thickness of a transistor’s silicon oxide film that would be required to provide the same electrical performance as the high-κ material being used.
¹⁰Residual charge (Qrem): Polarization remaining in ferroelectric or anti-ferroelectric thin films.

As shown in Figure 2, the capacitor composed of FE/DE showed a trade-off relationship in which the EOT greatly improved, but the Qrem increased rapidly. This was due to the sharp increase in the FE characteristics of the FE layer and the spontaneous polarization properties, causing a rise in the residual polarization. In contrast, the AFE/DE capacitor demonstrated a small improvement in EOT and a minimal increase in Qrem because the spontaneous polarization characteristics of the AFE were very low compared to the FE.

Figure 2.  A scatter graph showing the distribution of various Qrem and EOT characteristics of FE/DE and AFE/DE materials

In order to analyze the difference in the operation of DRAM cells according to residual polarization characteristics, the breakdown voltage (BV)¹¹, a major trade-off characteristic of capacity, and capacitance values of AFE/DE and FE/DE were evaluated (Figure 3). The two capacitors showed similar BV and capacitance values, but there was a significant difference recorded in DRAM cell operation (Figure 3a).

¹¹Breakdown voltage (BV): Minimum voltage at which part of the insulator is electrically destroyed and becomes conductive.

DRAM cells using the AFE/DE capacitor showed significantly less tWR¹² and FBC¹³ than DRAM cells with the FE/DE capacitor (Figure 3b). This is because when the data write operation time of the DRAM cell is checked through the tWR test, a relatively large amount of Qrem characteristics caused by the ferroelectricity of FE/DE act in the opposite polarity during the write operation. This hinders the subsequent DRAM operation, and the write operation does not function correctly. Therefore, when using FE and AFE as DRAM capacitors, it is important to consider not only the capacitance and BV characteristics (leakage current), but also the Qrem properties.

¹²Write recovery time (tWR): The appropriate amount of time required for data to be written to a DRAM cell; insufficient tWR will cause data errors during data read and write operations.
¹³Fail bit counts (FBC): Number of fail bits generated by one wafer during DRAM operation evaluation.

Figure 3. Results of selecting and evaluating AFE/DE and FE/DE with similar BV values and capacitance. (a) Scatterplot of BV and capacitance properties of FE/DE and AFE/DE (b) 12-inch wafer map for tWR fail bits in DRAM cells (c) correlation graph of FBC and Qrem properties.

In summary, this study investigated the electrical properties of FE/DE and AFE/DE materials and verified actual operation in DRAM cells. FE/DE materials demonstrated excellent potential for reducing EOT, but it was confirmed that the probability of fail bit generation during the tWR test increased rapidly due to its relatively high residual charge characteristics. On the other hand, AFE/DE is limited in reducing EOT, but the probability of fail bit generation during the tWR test is reduced due to the relatively low residual charge characteristics.

It was therefore concluded that AFE/DE is more suitable for use as a DRAM cell capacitor than FE/DE because residual charges must be strictly controlled for stable DRAM operation. To realize further miniaturization of DRAM technology, various new methods will need to be developed and verified to secure materials with strong FE characteristics.

For more information regarding RTC’s research, please visit the center’s research website (https://research.skhynix.com). The RTC operates the site to share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.

The post How Innovative Convergence Technology Is Tackling DRAM Scaling Challenges first appeared on SK hynix Newsroom.

¹Compute Express Link (CXL): PCIe-based next-generation interconnect protocol on which high-performance computing systems are based.

SK hynix’s SSM: Overcoming the Limitations of 3DXP

The phase-change memory (PCM)² product 3D XPoint (3DXP)³ gained significant attention for its high capacity, low latency, and byte-addressability. However, 3DXP has various shortcomings which hinder its application for CXL. For example, although 3DXP provides high capacity due to its small cell feature size (F) of 4F² and application of 2z⁴ nm process technology, further scaling is expected to face limitations. This is because PCM is susceptible to thermal disturbance (TDB)⁵ due to the smaller spaces between the cells, restricting its scaling potential. In terms of integration, since the 3DXP cell stack consists of a thick PCM, an ovonic threshold switch (OTS)⁶, and multiple electrodes, it has a very high aspect ratio (AR)⁷. In addition, PCM and OTS consist of “floppy” chalcogenides of which 20-30% are void or defect, which can lead to a leaning or wiggling phenomenon.

²Phase-change memory (PCM): A technology which enables nonvolatile electrical data storage at the nanometer scale. A PCM device consists of a small active volume of phase-change material placed between two electrodes. A common PCM material is germanium-antimony-tellurium (GeSbTe).

³3D XPoint (3DXP): A non-volatile phase change technology that serves as both memory and storage.

⁴2z: The third generation of 20 nm process technology in which “z” refers to the lower third number range of the 20 nm class, which covers 20 nm-29 nm. The letters “x”, “y” and “z” are used to refer to the upper, middle, and lower thirds, respectively, of the relevant process technology class such as 10 nm, 20 nm etc.

⁵Thermal disturbance (TDB): Inadvertently altering the state of a cell by programming another cell in its vicinity.

⁶Ovonic threshold switch (OTS): A two-terminal symmetrical voltage sensitive switching device which, after being brought from the highly resistive state to the conducting state, returns to the highly resistive state when the current falls below a holding current value.

⁷Aspect ratio (AR): The ratio of height to width. A high aspect ratio means that the structure is narrow but tall.

With the limitations of 3DXP clear to see, SK hynix shared the excellent array operation performance of its 20 nm SSM for the first time at IEDM 2022. SSM has a single cell stack, consisting of a cell material (dual function material), two electrodes, and two metal wires, which acts as both memory and selector in bi-directional operations. This simple stack enables SSM to overcome the scaling limitations of conventional PCM.

Figure 1. Cross section transmission electron microscopy (TEM) of an SSM cell stack (left) and the plan-view scanning electron microscopy (SEM) of eight mats making up a 32 Mb array (right)

It is widely known that chalcogenide-based devices such as 3DXP have a large Vt distribution. Figure 2 shows that SSM successfully obtained a suitable read window margin (RWM)⁸, the main hurdle for high density array operation, using cell stack materials engineered with the help of bipolar write operations. Sufficient RWM can be obtained even below a write pulse of 20 nanoseconds (ns) for both set and reset states, and at a much lower write current than conventional 3DXP. This guarantees extremely low write latency and power consumption. Moreover, the low write current and short write pulse means that SSM is placed under significantly less operational stress than 3DXP. Therefore, SSM offers superior write cycle endurance of up to 10 million (1E7) cycles.

⁸Read window margin (RWM): The threshold voltage (Vt) interval (ΔVt) at distribution tails. When using a chalcogenide material such as PCM, it has a Vt distribution similar to DRAM or NAND. The Vt interval between the Vt distribution of 0 and 1 is regarded as the sensing margin, or the read window margin.

Figure 2. Innovative cell stack engineering and material development enabled SSM to achieve a larger RWM than 3DXP

Determining the Composition Distribution of SSM

The fundamental operational mechanism of SSM is thought to be related to the atomic migration model. The vertical composition distribution of dual function material (DFM) cells in SSM can be detected by energy dispersive spectroscopy (EDS)⁹. As seen in Figure 3, clear differences are detected in the top, middle, and bottom layers when the set and reset bias are applied in opposite directions. In this case, an increase in atomic migrations is detected when the atoms have more electronegativity¹⁰. However, the atomic migration model combined with conventional transport theory fails to explain the voltage difference. Further research is therefore needed to come up with a theoretical explanation for this phenomenon.

⁹Energy dispersive spectroscopy (EDS): A chemical microanalysis technique which detects X-rays emitted from the sample during bombardment by an electron beam to identify the elemental composition of the sample.

¹⁰Electronegativity: The ability of an atom to attract shared electrons when forming a chemical bond.

Figure 3. The vertical composition distribution of DFM cells in SSM detected by EDS

Due to the elimination of phase change material, SSM showed no write disturbance (thermal disturbance) which can help improve the total system power consumption and performance. In addition, scaling is expected to have a smaller effect on SSM cell characteristics than found in 3DXP. When the cell critical dimension (CD), which refers to the cell width or length, is reduced from 18 nm to 15 nm in the same pitch, the change of voltage is relatively minimal. In light of this, SSM is expected to have more scalability than 3DXP.

Figure 4. Specification comparison of 3DXP and SSM (Source: T.Kim et al, IEDM2018)

Application With CXL & VSOM in the Future

SK hynix has demonstrated the successful array operation of 20 nm SSM for high-density memory applications as a successor to 3DXP. SSM outperforms 3DXP in terms of write latency, cell power consumption, and reliability. Moreover, the lower aspect ratio seems promising for the scaling of nodes below 1z nm. When coupled with its excellent latency and low power consumption, SSM is well-placed to make up for the deficiencies of 3DXP and be applied to CXL memory and vertical SOM in the future.

For more information regarding RTC’s research, please visit the center’s research website (https://research.skhynix.com). The RTC operates the site to share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.

The post How Selector-Only Memory Emerged as the Leading Solution for CXL first appeared on SK hynix Newsroom.

In this EE Times article, Myung-hee Na, vice president of SK hynix’s Revolutionary Technology Center (RTC), reveals how emerging memory solutions such as chalcogenide-based memories are being developed for the advanced technologies of today.

SK hynix is leading this industry innovation through the development of its chalcogenide-based selector-only-memory (SOM) to improve performance and simplify processes. Unlike previous memory solutions such as phase-change memory (PCM), this new SOM acts as both memory and selector in bi-directional operations.

Despite SOM’s promise, it does face some technical challenges which has led SK hynix to research the feasibility of vertical SOM (VSOM). VSOM opens the door to the development of ultra-high density memory solutions but significant material innovations are required to realize its potential.

Na also writes about how the “Beyond Memory” era can truly begin with memory solutions that break the boundaries between computation and memory. In this regard, SK hynix’s RTC has been researching analog-compute in memory (ACIM) as it has the potential for simultaneous computation and storage due to its non-volatile memory characteristics.

As the introduction of emerging memory solutions requires a whole new memory R&D ecosystem, Na concludes the article with calls for industry-wide collaboration across this new ecosystem to fully realize the potential of innovative memory products.

To find out more about these new memory solutions, read the full EE Times article here: How Emerging Memory Supports Next-Gen Computing in the Data Explosion Era

The post How Emerging Memory Supports Next-Gen Computing in the Data Explosion Era first appeared on SK hynix Newsroom.