Rulebreakers - SK hynix Newsroom

[Rulebreakers’ Revolutions] How SK hynix’s SOM Paves the Way for Next-Gen Memory in the AI Era

user — Wed, 26 Mar 2025 06:00:35 +0000

Challenging convention, defying limits, and aiming for the skies, rulebreakers remake the rules in their quest to come up with groundbreaking solutions to problems. Following on from SK hynix’s “Who Are the Rulebreakers?” brand film, this series showcases the company’s various “rulebreaking” innovations that have reshaped technology and redefined new industry standards. This final episode of the series will cover SK hynix’s development of Selector-Only Memory (SOM).

AI and high-performance computing (HPC) are evolving at an unprecedented pace, pushing traditional memory technologies such as DRAM and NAND flash to their limits. To meet the growing demands of the AI era, the industry is exploring emerging memory technologies which go beyond traditional memory.

Among these new memory technologies, storage-class memory¹ (SCM) has emerged as a key development as it can bridge the performance gap between DRAM and NAND flash. Recognizing the potential of SCM, SK hynix has developed selector-only memory² (SOM), a groundbreaking innovation that redefines SCM and strengthens the company’s AI memory portfolio.

¹Storage-class memory: A class of emerging non-volatile memory technologies that combines the speed of DRAM with the persistent storage capabilities of NAND flash. It bridges the gap between DRAM and NAND flash in terms of performance, cost, and storage capacity.
²Selector-only memory (SOM): A cross-point memory device featuring a chalcogenide-based film which can perform both selector and memory functions.

This final episode of  Rulebreakers’ Revolutions  explores the journey behind SOM’s development, the key role of SK hynix’s rigorous R&D approach, and the implications for the future of AI and HPC.

The Mission: Going Beyond Traditional Memory With Next-Gen SCM

The AI era has sparked a data explosion. AI systems, from large language models³ (LLMs) to multimodal AI⁴, require high-performance memory to rapidly access and process this vast amount of data and perform complex computations. This next-generation performance must be balanced with affordability and energy-efficiency, placing further pressure on memory technologies.

³Large language model (LLM): Advanced AI systems trained on vast amounts of text data to understand and generate human-like text based on the context they are given.
⁴Multimodal AI: Machine learning models capable of processing and integrate different types of data, including text, audio, and video.

To meet these increasing demands, HPC systems are transitioning from traditional CPU-centric models to memory-centric architectures. By supporting data processing directly within memory, these memory-centric systems can minimize data movement to ultimately improve system performance and efficiency.

Amid this shift, the industry is exploring new memory technologies which can surpass the capabilities of traditional memory. Among them, SCM has emerged as a promising solution by bridging the performance gap between DRAM and NAND flash. As a non-volatile memory, SCM combines the speed and cost-efficiency of DRAM with the high capacity of NAND flash. Additionally, the advent of CXL^®⁵ technology has enabled seamless connections between memory and devices such as CPUs, GPUs, and accelerators, creating new opportunities for SCM adoption in advanced computing.

⁵Compute Express Link^®(CXL^®): A next-generation interface that connects the CPU, GPU, memory, and other components to efficiently enhance the performance of high-performance computing systems.

Recognizing the capabilities of the technology, SK hynix took on the challenge of developing a next-generation SCM product—SOM—which could revolutionize the industry.

SK hynix’s SOM goes beyond traditional memory, breaking the barriers to next-generation memory

Beyond 3DXP: Rigorous R&D and Collaboration Unlock SOM

Before developing SOM, SK hynix had made great progress with an alternative SCM technology—3D XPoint (3DXP). Developed in the mid-2010s, 3DXP was a non-volatile storage technology that used phase-change memory (PCM)⁶ to store data through changes in material resistance states. It employed a transistor-less, cross-point architecture⁷ featuring selectors⁸ and memory cells placed at the intersection of perpendicular wires. By stacking 3DXP cells in a three-dimensional architecture without transistors, the product offered high memory density.

⁶Phase-change memory (PCM): A technology which enables non-volatile electrical data storage at the nanometer scale. PCM memory switching involves heating materials so they switch between amorphous and crystalline states, which correspond to the binary digits 0 and 1, respectively.
⁷Cross-point architecture: A memory architecture where data is stored at the intersection, or “cross-point”, of two or more lines in a grid-like structure.
⁸Selector: A device in a memory array that regulates the flow of current to and from a memory cell. This enables precise access to a specific cell while blocking unwanted paths for more accurate read and write operations.

Despite the potential of 3DXP, SK hynix identified challenges regarding the product’s scalability beyond 20 nm process technology. As a result, the company switched its attention to an alternative next-generation SCM product.

The company set about developing SOM, a groundbreaking cross-point memory device that uses a single chalcogenide⁹ -based film, known as dual-functional material (DFM), to perform both selector and memory functions. Compared to 3DXP, SOM eliminates the need for the separate selector and PCM setup. Instead, selectors in SOM are deployed without standalone memory cells to improve selector functionality. Moreover, SOM utilizes an optimized cross-point array with lower cell stack aspect ratios¹⁰ for better scalability and higher memory density.

⁹Chalcogenide: A chemical compound consisting of at least one chalcogen anion, such as sulfur, and an electropositive element, such as metal.
¹⁰Aspect ratio: Height-to-width ratio of memory cells.

One of the biggest changes from 3DXP was the inclusion of DFM in place of phase-change material. As a result of this switch, SOM offers advanced specifications. Firstly, the write speed is significantly improved as DFM, unlike PCM, does not require time to perform phase changes. While PCM required a high write current for joule heating during phase transitions, the use of DFM significantly reduced the necessary write current. In addition, DFM offers increased stability when operating at high temperatures, reducing thermal disturbance¹¹. DFM’s improved heat resistance also ensures it offers enhanced cyclic endurance compared to PCM, boosting overall durability.

¹¹Thermal Disturbance: A phenomenon where heat generated while programming one memory cell unintentionally affects the state of neighboring cells due to heat diffusion, potentially disrupting their data integrity.

SOM replaces the phase-change material used in 3DXP with DFM

The successful development of SOM would not have been possible without SK hynix’s rigorous approach to R&D and smooth internal collaboration. For example, the company discovered DFM during research on chalcogenide-based selector and memory materials. By applying a new bipolar operation instead of the conventional unipolar operation, the team found it could achieve both selector and memory characteristics simultaneously.

The company’s R&D approach also enabled a significant reduction in SOM’s power consumption compared to pre-development expectations. When conventional optimization approaches proved insufficient, this prompted a radical reexamination of materials, design, and operational algorithms. In response, various research teams came together to collaborate on the project and develop new approaches. They tested the application of new materials and operational techniques through simulations, addressing any potential issues. This meticulous process cut power consumption by approximately one-third from initial predictions, a crucial advancement in the development of SOM.

Unveiling the World’s Smallest SOM

SK hynix has successfully developed the world’s smallest SOM, the first fully integrated¹² 16nm half-pitch¹³ SOM. This revolutionary achievement in the SCM field was presented at the prestigious 2024 IEEE Symposium on VLSI Technology and Circuits (2024 VLSI Symposium).

¹²Fully integrated: Complete integration of circuits and manufacturing processes at the cell array level, unlike basic single-cell prototypes in academic research.
¹³Half-pitch: Half of the minimum center-to-center distance between interconnect lines in a semiconductor.

Compared to 3DXP, SOM offers a reduction in write speed from 500 nanoseconds (ns) to 30 ns and write current, which dropped from 100 microamps (µA) to 20 µA. In addition, cyclic endurance increased from 10 million to over 100 million cycles, highlighting SOM’s increased durability. SOM was also shown to have advanced persistency, the ability to retain data under extreme conditions, as tests proved it could retain data for over 10 years at 125°C.

SOM offers outstanding capabilities from rapid write speed to advanced persistency

Significantly, the 16nm SOM is the smallest, most scalable and high-performing cross-point memory solution on the market. As the AI landscape continues its evolution, the successful development of SOM strengthens SK hynix’s AI memory leadership, complementing products such as HBM, AiMX, and CXL Memory Module (CMM)-DDR5.

Looking forward, the research behind SOM will contribute to broader advancements in next-generation memory technology. Its impact extends to the growing field of heterogeneous integration, enabling innovative system integration approaches that cater to AI data centers and diverse AI solution providers. As computing architectures shift towards memory-centric computing, SOM’s technological breakthroughs will play a crucial role in shaping the future of AI and HPC.

Rulebreaker Interview: Myoungsub Kim, Global Revolutionary Technology Center (RTC)

To find out more about the company’s innovative approach to SOM development, the SK hynix Newsroom spoke with Myoungsub Kim of the Global Revolutionary Technology Center (RTC), which conducts R&D of next-generation semiconductors. Kim discusses the major challenges faced when developing SOM as well as the rulebreaking mindset adopted by employees.

What were the major challenges that you faced during the SOM development process?

“The main challenge was making the decision to become a first mover and begin R&D of the world’s first half-pitch 16nm SOM. This process involved transitioning from focusing on conventional PCRAM-based 3DXP memory while also preparing for the scalability and performance advantages of SOM, despite the uncertainties involved.”

What is your proudest moment when leading SOM R&D?

“At the 2022 IEEE International Electron Devices Meeting (IEDM) conference, we were the first in the industry to claim the potential performance and scalability advantages of SOM. This led to my proudest moment when we were able to prove these claims at the 2024 VLSI Symposium. We presented our research on the world’s first fully process-integrated half-pitch 16nm SOM, achieving the industry’s smallest size.”

What aspects of SK hynix’s corporate culture help foster creativity and overcome limitations?

“Above all, SK hynix’s new Code of Conduct is founded on SKMS’s VWBE¹⁴ and SUPEX¹⁵ principles. In particular, the pursuit of ‘bar raising,’ which encourages employees to continually obtain higher standards in the pursuit of excellence, and the ‘one team’ approach, which fosters collaboration as a unified team, have enabled us to continuously showcase our creativity and overcome limitations.

¹⁴Voluntarily, Willingly, Brain, Engagement (VWBE): One of the employee values emphasized by SK Management System (SKMS).
¹⁵SUPEX: An SK hynix philosophy carrying the meaning “super excellent,” SUPEX represents the company’s mission to achieve the highest possible levels of achievement.

“To sum up, I believe there is a recipe for innovation: embrace new changes with a spirit of challenge, experiment in the face of uncertainty without fear of failure, and learn with flexibility.”

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

[Rulebreakers’ Revolutions] How SK hynix’s Server DRAM Validation Process Succeeds in a Diverse Server CPU Market

[Rulebreakers’ Revolutions] Flexible & Collaborative eSSD Virtualization Development for Today’s Data Centers

[Rulebreakers’ Revolutions] How SK hynix’s Design Innovations Pushed GDDR7 to New Limits of Speed

[Rulebreakers’ Revolutions] How CXL Tech Expands Data Center Memory Scaling Boundaries in the AI Era

The post [Rulebreakers’ Revolutions] How SK hynix’s SOM Paves the Way for Next-Gen Memory in the AI Era first appeared on SK hynix Newsroom.

[Rulebreakers’ Revolutions] How CXL Tech Expands Data Center Memory Scaling Boundaries in the AI Era

user — Fri, 24 Jan 2025 00:00:12 +0000

Challenging convention, defying limits, and aiming for the skies, rulebreakers remake the rules in their quest to come up with groundbreaking solutions to problems. Following on from SK hynix’s “Who Are the Rulebreakers?” brand film, this series showcases the company’s various “rulebreaking” innovations that have reshaped technology and redefined new industry standards. This article will delve into SK hynix’s development of CXL technology.

The world runs on data—a ceaseless tide of ones and zeros surging through networks, powering everything from streaming services to AI. To handle this data deluge, data centers must employ more advanced memory solutions that meet ever-growing performance demands.

However, traditional methods of scaling memory are facing limitations. The constraints of processors and memory technologies, coupled with escalating costs and power consumption for data centers, have highlighted the need for a revolutionary approach. Enter Compute Express Link^® (CXL^®), a transformative memory interconnect technology designed to tackle the challenges of the AI era.

This Rulebreakers’ Revolutions  episode will cover SK hynix’s development of CXL solutions, detailing how the company overcame obstacles, such as a lack of industry specifications, to become a leader in the CXL field and a key contributor to the CXL ecosystem.

Mission: Harnessing New Interconnect Tech for Memory Scaling

In the AI era, data centers need to continuously expand their memory capacity to handle ever-growing volumes of data. However, scaling memory capacity through traditional methods is becoming prohibitively expensive and inefficient. For example, adding terabyte (TB)-scale memory to a single CPU system can significantly increase the total cost of ownership¹ (TCO) and power consumption. Attempting to address this by increasing memory channels or integrating higher capacity memory often results in even greater power usage and heat generation, further inflating cooling system and management costs. This has underlined the need for innovative memory system designs which can process data faster, more efficiently, and cost effectively.

¹Total cost of ownership: The complete cost of acquiring, operating, and maintaining an asset, including purchase, energy, and maintenance expenses.

Data center memory capacity needs to increase to handle the growing demands of the AI era

Over the past decade, the industry has been developing new memory interconnect technologies to meet this market demand. Memory interconnect technology refers to the method by which processors exchange data with memory, playing a critical role in determining the speed and efficiency of data processing. In traditional memory architectures, memory is physically connected to a nearby single processor, which can lead to an over-provision of memory resources when applications are not using the memory. New memory interconnect technologies such as CXL can overcome this issue by allowing multiple processors to share memory for improved efficiency.

This has led to great interest in CXL, however developing the technology would prove challenging as there was no precedent for the process and initially no industry-established specifications. Without the JEDEC² specifications which are generally provided for DRAM products, the development process for CXL was fundamentally more complex than usual.

²JEDEC Solid State Technology Association: With over 350 member companies, JEDEC is the global leader in developing open standards for the microelectronics industry.

Faced with having to develop new CXL products without industry specifications to break the barriers of memory scaling, SK hynix tapped into its internal expertise and collaborated with industry partners.

Into the Unknown: Developing Pioneering CXL Tech From Scratch

Following the introduction of CXL in 2019, SK hynix soon recognized the technology’s capability to meet ever-growing memory scaling needs. As an open industry-standard interconnect, CXL unifies the interfaces of different system devices such as memory, storage, and processors. It supports features such as memory sharing, allowing multiple processors to access the same memory for improved data sharing, and memory pooling, in which memory from a common pool is assigned to processors for enhanced efficiency. Furthermore, CXL also enables memory switching, allowing hundreds of devices such as processors to share memory resources while independently processing data.

In addition to these innovative features, SK hynix became further convinced of CXL’s immense potential after observing increased market and customer commitment to the technology and identifying its promise in addressing technical and cost challenges. However, the company had to begin the project by overcoming a significant obstacle—a lack of industry specifications. SK hynix therefore soon set about developing its own basic requirement document after participating in CXL standardization activities and working with customers to define specifications. The company also collaborated with CXL controller companies to define controller requirements for the specifications document. Furthermore, the company has worked with JEDEC and the CXL Consortium³ to enhance DRAM-related specifications for industry CXL standards.

³CXL Consortium: An open industry standards group that develops technical specifications for CXL.

SK hynix’s CXL technology overcomes memory scaling challenges by expanding system capacity and bandwidth

Having helped set industry standards and develop relevant specifications, the company has accelerated its CXL development. For this process, SK hynix has identified key criteria to meet customer requirements—cost efficiency, high capacity, optimized bandwidth, and reliability.

First, cost efficiency is paramount in CXL development. To counteract the high cost of CXL controllers, it is crucial to minimize the costs of memory media such as modules. As high capacity is essential to facilitate large-scale data processing, the company determined CXL memory should offer storage two to four times larger than existing DDR products. Furthermore, bandwidth design must be optimized to utilize the full performance potential of CXL modules. Finally, reliability and data integrity must match the high standards of the host memory to earn customer trust.

To meet these criteria, multiple departments across SK hynix are working on making terabyte-scale memory more affordable and efficient. This includes pioneering memory pooling technologies that enable resource sharing among multiple devices and developing NMP⁴ technologies to handle data close to its source. These innovations are poised to deliver significant benefits to applications such as high-performance computing (HPC), in-memory databases, and AI.

⁴Near-memory processing (NMP): A technique that performs computations near data storage, reducing latency and boosting performance in high-bandwidth tasks like AI and HPC.

Through these efforts, SK hynix has been able to advance the development of groundbreaking CXL products which are set to revolutionize the memory field.

SK hynix’s Growing Product Lineup Driving the Future of CXL

Since developing its first DDR5-based CXL sample in 2022, SK hynix has been strengthening its CXL portfolio which includes the innovative CXL Memory Module-Double Data Rate 5 (CMM-DDR5). Leveraging high-speed PCIe Gen5 connections, CMM-DDR5 ensures smooth and rapid data processing. Available with up to 128 GB of storage, CMM-DDR5 also offers the high capacity required for the demands of today’s AI and HPC applications. In addition, the module boasts high levels of power efficiency and security.

Real-world performance tests highlight the transformative impact of CMM-DDR5. The product can expand system bandwidth by up to 82% and capacity by up to 100% compared to systems equipped with only DDR5 DRAM. Tests also showed how AI workloads experienced a 31% increase in token per second performance and that HPC enjoyed a 33% improvement in throughput efficiency. As well as providing outstanding performance, CMM-DDR5 has aligned with both JEDEC and CXL Consortium standards. Currently, the verification and certification of CMM-DDR5 is being carried out by customers as the product moves closer to mass production.

SK hynix’s CXL-based CMM-DDR5 enhances AI and HPC performance

SK hynix’s other CXL solutions include Niagara 2.0, an integrated hardware and software solution that allows multiple hosts to efficiently share large memory pools to minimize unused or underutilized memory. Furthermore, CXL Memory Module-Ax (CMM-Ax), a high-performance memory module optimized for computational workloads, is notable for improving AI and data center efficiency.

Beyond hardware advancements, SK hynix has developed the Heterogeneous Memory Software Development Kit (HSMDK) to maximize the potential of its CXL memory. This software toolkit has even been integrated into Linux’s operating system, further enhancing its accessibility and usability. The development of both hardware and software solutions as well as its standardization efforts highlights how SK hynix is committed to creating a thriving CXL ecosystem.

Rulebreaker Interview: “Thomas” Wonha Choi, Next-Gen Memory & Storage

In an interview with the SK hynix Newsroom, Distinguished Engineer⁵ (DE) “Thomas” Wonha Choi of Next-Gen Memory & Storage discussed the company’s rulebreaking mentality for developing CXL technology. Responsible for standardization efforts with JEDEC and the CXL Consortium and pathfinding next-generation memory such as CXL, Choi spoke about CXL’s development and its future impact.

⁵Distinguished Engineer: Senior SK hynix engineers who excel in their fields and are tasked with solving technical challenges and mentoring the next generation.

When did you and your team demonstrate outside-the-box thinking while developing industry-leading CXL technologies?

“During CXL development, we applied the working principles of SK hynix’s VWBE⁶ philosophy and tapped into experiences developing DRAM and NAND products to proactively propose working methods and initial CXL requirements to customers. Presenting these requirements in advance created more opportunities for technical deep dives into CXL, eventually leading to the successful development of our first CXL memory product.

⁶Voluntarily, Willingly, Brain, Engagement (VWBE): One of the employee values emphasized by SK Management System, or SKMS.

“Personally, I anticipated how the standardization and validation methods would merge DRAM and NAND approaches, and independently proposed and refined DRAM-related features within the CXL Consortium. Through these efforts, I am proud to have contributed to the company’s initial CXL deployment strategy. It shows that, even when going into the unknown as we did for CXL, we harnessed our spirit of innovation and resilience to find answers to new problems.

“Additionally, I volunteered for demanding positions at JEDEC and the CXL Consortium, thereby contributing to elevating the company’s stature in standardization efforts.”

How do you see CXL evolving in the future AI ecosystem?

“CXL is expected to establish an ecosystem that enables the sharing of ultra-high-capacity memory. For CXL to expand further in the AI era, it will need to support computing nodes, secure cost-effective memory over 1 TB, provide bandwidth as and when it’s needed, and maintain reliability and security at the memory level. This will help reduce TCO and improve memory utilization within system platforms.

“Building such an ecosystem is not something SK hynix can achieve alone; it requires active collaboration with GPU and CPU manufacturers, CXL controller and switch vendors, and even CXL intellectual property (IP) companies. We plan to work with these organizations to further strengthen the CXL ecosystem.”

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

[Rulebreakers’ Revolutions] How SK hynix’s Server DRAM Validation Process Succeeds in a Diverse Server CPU Market

[Rulebreakers’ Revolutions] Flexible & Collaborative eSSD Virtualization Development for Today’s Data Centers

[Rulebreakers’ Revolutions] How SK hynix’s Design Innovations Pushed GDDR7 to New Limits of Speed

The post [Rulebreakers’ Revolutions] How CXL Tech Expands Data Center Memory Scaling Boundaries in the AI Era first appeared on SK hynix Newsroom.

[Rulebreakers’ Revolutions] How SK hynix’s Design Innovations Pushed GDDR7 to New Limits of Speed

user — Fri, 27 Dec 2024 06:00:53 +0000

Challenging convention, defying limits, and aiming for the skies, rulebreakers remake the rules in their quest to come up with groundbreaking solutions to problems. Following on from SK hynix’s “Who Are the Rulebreakers?” brand film, this series showcases the company’s various “rulebreaking” innovations that have reshaped technology and redefined new industry standards. This episode will focus on how the company’s design innovations enabled it to develop the industry-leading GDDR7.

“It always seems impossible until it’s done.” This famous quote from Nelson Mandela underlines the importance of continually overcoming seemingly unsurmountable challenges to achieve a goal, an approach which is essential to succeed in the rapidly evolving semiconductor sector.

As industry standards are consistently updated, semiconductor companies are tasked with finding the necessary technical solutions to comply with these criteria. SK hynix has a long track record in this area, as recently exemplified by its ability to meet the increased speed standards for the latest GDDR¹ graphics DRAM, GDDR7.

¹Graphics DDR (GDDR): A standard specification of graphics DRAM defined by the Joint Electron Device Engineering Council (JEDEC) and specialized for processing graphics more quickly. It is now one of the most popular memory chips for AI and big data applications.

This episode of Rulebreakers’ Revolutions will focus on how the company’s design and technical innovations coupled with cross-departmental collaboration enabled it to develop the industry-leading GDDR7 with the highest levels of speed.

The Mission: Finding Technical Solutions to Meet GDDR7 Speed Standards

Traditionally used in graphics and gaming, GDDR DRAM is now applied to a broader range of fields including AI, high-performance computing (HPC), and autonomous driving. This is due to its parallel processing capability and advanced specifications such as high speed and power efficiency which have increased with each generation.

To satisfy increased industry speed standards for GDDR7, SK hynix derived key design and technical innovations

The standards for GDDR memory are set by the Joint Electron Device Engineering Council (JEDEC), the global standardization body for the microelectronics industry. These include ever-increasing speed requirements, progressing for example from GDDR5’s data rate of 5–10 gigabits per second (Gbps) per pin to GDDR6’s speed of 14–20 Gbps. For GDDR7, JEDEC set a target data rate range of 24 –32 Gbps, placing additional pressure on semiconductor companies to adapt to meet the latest specifications.

One of the main changes in the GDDR7 standards to facilitate these rapid speeds was the introduction of a new signaling interface. For the first time in a JEDEC standard for DRAM products, GDDR7 called for the use of the innovative PAM² method for high frequency operations. Unlike the traditional NRZ³ interface which uses two levels to transmit data, the new PAM3 system employs three levels, enabling a higher data transmission rate for improved performance.

²Pulse amplitude modulation (PAM): A signaling process that encodes a continuous analog signal into discrete analog pulses by representing the signal’s amplitude as a binary number at a specific time.
³Non-return-to-zero (NRZ): A simple signaling interface which sends information over two levels of a signal. As the name suggests, the signal does not return to zero during between bits.

By using three levels to transmit data, PAM3 offers faster data transmission rates than the two-level NRZ interface

To support the required rapid data rate specifications and PAM3 interface, GDDR7 products needed to incorporate several new cutting-edge technologies and design innovations. In addition to these technical challenges, SK hynix also had to overhaul the testing approach it used for GDDR6. During these tests, the company faced difficulties in ensuring the same performance in real-world system environments as it achieved in the device testing phase.

Tasked with devising technological innovations and rethinking its testing approach, SK hynix tapped into its design knowhow, company-wide expertise, and well-established ability to take on new challenges.

Design Innovations, Collaboration, & New Testing Approach to Reach Speed Goals

SK hynix drew from its experience developing GDDR6 and embraced cross-departmental collaboration for GDDR7, enhancing several key design elements and integrating advanced technologies to hit the product’s ambitious speed targets.

In a company-first for a mass-produced DRAM product, SK hynix integrated a T-coil⁴ inductor following multiple tests and evaluations to optimize its metal layers. T-coils improve signal integrity by mitigating high-frequency losses, thereby expanding the data eye margin⁵ and facilitating reliable high-speed data transfer.

⁴T-coil: An inductive circuit commonly used in analog and radio frequency electronics to improve signal integrity and overall circuit performance.
⁵Data eye margin: The safety buffer within a digital signal’s eye diagram, a representation of signal integrity, that ensures reliable data transmission in high-speed communication systems.

SK hynix derived several design innovations to attain GDDR7’s increased speed standards

SK hynix also implemented an established and robust write clock (WCK) framework, a high-speed clock signal dedicated to data input and output operations. This design allows for precise timing control for data transfers, resulting in higher data rates. To maintain stable data transmission at high speeds, the company also increased the number of heat-dissipating substrate layers from four to six and applied EMC⁶ as the packaging material to reduce thermal resistance.

⁶Epoxy Molding Compound (EMC): An essential material for semiconductor packaging that seals chips to protect them from water, heat, and shock damage.

As part of efforts to improve its testing environment and ensure consistent performance, the company put together a specialized taskforce. This team established an evaluation, analysis, and management environment that could ensure consistency between simulation results and actual system implementation. Additionally, the taskforce outlined key design parameters to secure characteristics in system environments and developed circuit schemes for high-speed operation.

Regarding PAM3 testing, SK hynix first confirmed the feasibility of PAM3 operation by producing a test chip. Moreover, the company needed a solution to test PAM3 on existing mass-produced devices which use NRZ signaling. Through collaboration with related departments and test working group activities, the company carried out functional verification and mass production testing of PAM3 using NRZ signaling equipment. This enabled SK hynix to extend GDDR7’s multi-level I/O verification capabilities without requiring completely new testing infrastructure.

Aside from innovations related to improving speed or integrating PAM3 signaling, SK hynix also secured a competitive edge in power efficiency for its GDDR7 by supporting heterogeneous power modes. Through this advancement which allowed the product to function at lower voltages, the company was able to achieve significant power savings.

Redefining Standards in Speed & Power Efficiency

Boasting a rapid data rate and data processing speed, the GDDR7 offers industry-leading specifications

As a result of its strong internal collaboration, ability to overcome technological obstacles, and previous GDDR experience, SK hynix was able to develop the industry-leading GDDR7 in July 2024. The groundbreaking product achieved an industry-leading data rate of 32 Gbps—over 60% faster than the previous generation—which can rise to up to 40 Gbps depending on the circumstances.

When adopted for high-end graphics cards, SK hynix’s GDDR7 offers a data processing speed of more than 1.5 TB per second, equivalent to processing 300 Full HD movies each with a capacity of 5 GB, in a second. Overall, the product offers a 74% reduction in thermal resistance compared with the previous generation.

In addition to improved speed and heat dissipation, SK hynix enhanced the product’s power efficiency by more than 50% compared with the previous generation. This is particularly crucial to ensure GDDR7 can maintain its high performance for demanding applications such as AI while minimizing energy consumption.

These performance breakthroughs position SK hynix’s GDDR7 as the world’s highest-spec GDDR7. The development ensured SK hynix not only advanced the product’s characteristics but also established high-speed features that will benefit other DRAM products, such as mobile memory, bolstering its leadership in high-speed solutions.

Rulebreaker Interview: Jinyoup Cha, Graphic Design

The SK hynix Newsroom spoke with Jinyoup Cha, team leader of Graphic Design, a team in the DRAM Design department responsible for designing graphic DRAMs, to learn more about the company’s innovative approach to GDDR development. Having led the design of GDDR7, Cha is well-positioned to discuss the challenges of continually improving speed characteristics and the goals for next-generation GDDR memory.

As the generations of DRAM products advance, JEDEC’s standard requirements for speed have increased significantly. What do you see as the biggest obstacle in achieving such continuous speed improvements?

“In ensuring speed characteristics, there are limitations to achieving this solely through design schemes. It can only be accomplished when the latest technological elements—such as devices, specifications, testing, and packaging—are integrated with design innovations.

“The most challenging aspects are continuously monitoring market requirements and preemptively defining the technologies that need to be developed. Regarding the latter point, it is essential to prepare the necessary fundamental technologies through collaboration with related departments.”

As a team leader, what areas do you focus on to encourage your team to consistently embrace creativity and surpass limitations?

“To achieve the given objectives, I focus on setting a direction through discussions with team members and boldly pursuing new tasks. No matter how many challenges are on the road ahead, we see them as an opportunity for us to sharpen our skills and redefine our limits.

“In particular, since new tasks cannot be handled solely by the design team, it is necessary to collaborate with related departments. Therefore, I strive to create an environment where team members can voluntarily cooperate with other departments.”

As SK hynix prepares to develop next-generation GDDR products, could you briefly introduce the goals or direction that your department aims to address?

“We aim to maintain our position as the leader in the graphics memory market in terms of technological competitiveness. Along with the expansion of the graphics market, we plan to achieve the No. 1 market share through superior product competitiveness, thereby contributing to company growth.”

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

[Rulebreakers’ Revolutions] How SK hynix’s Server DRAM Validation Process Succeeds in a Diverse Server CPU Market

[Rulebreakers’ Revolutions] Flexible & Collaborative eSSD Virtualization Development for Today’s Data Centers

The post [Rulebreakers’ Revolutions] How SK hynix’s Design Innovations Pushed GDDR7 to New Limits of Speed first appeared on SK hynix Newsroom.

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

user — Mon, 30 Sep 2024 00:00:29 +0000

Challenging convention, defying limits, and aiming for the skies, rulebreakers remake the rules in their quest to come up with groundbreaking solutions to problems. Following on from SK hynix’s “Who Are the Rulebreakers?” brand film, this series showcases the company’s various “rulebreaking” innovations that have reshaped technology and redefined new industry standards. This third episode covers the adoption of the 6-phase RDQS design scheme to HBM3E.

“Design is not just what it looks and feels like. Design is how it works.” These words of Apple Co-Founder Steve Jobs emphasize the crucial role design plays in the functionality of products. This is particularly true in the semiconductor industry, where design involves defining the chip’s architecture, purpose, and circuit layout to ultimately enable its smooth performance.

The chip design scheme can also play a key role in overcoming challenges. When faced with scaling and data transmission limitations while developing HBM3E¹, SK hynix introduced a pioneering 6-phase read-data-strobe (RDQS) design scheme. This world-first application enabled HBM3E to make huge strides in performance from its predecessor while maintaining the same packaging size.

This episode of Rulebreakers’ Revolutions reveals how SK hynix made the groundbreaking leap from the previous 4-phase to the 6-phase RDQS scheme, allowing the company to develop the world’s best-performing HBM3E with enhanced capacity and increased reliability.

¹HBM3E: The fifth-generation and latest High Bandwidth Memory (HBM) product. HBM is a high-value, high-performance product that revolutionizes data processing speeds by connecting multiple DRAM chips with through-silicon via (TSV).

Overcoming Scaling & Data Transmission Limitations in HBM3E

While there are challenges when developing any semiconductor product, the development and manufacturing process for HBM solutions comes with its own set of specific issues. For example, there are difficulties when mass-producing HBM due to its use of through-silicon via (TSV) for chip stacking. When developing HBM3E, SK hynix found that TSV presented obstacles to its goal of maintaining the same packaging size as the previous generation HBM3 while increasing capacity.

Originally applied in SK hynix’s first-generation HBM in 2013, TSV involves drilling microscopic holes in a DRAM chip to connect the electrodes that vertically penetrate the holes of the chip’s upper and lower layers. Due to these holes, TSV signals occupy a significant amount of space in peripheral circuits². As these circuits typically account for 20-30% of the total area in a memory product, the large number of TSV signals in HBM products hinders scaling efforts—resulting in a need for TSV area optimization.

SK hynix also targeted advancing HBM3E’s data transmission characteristics during development to ensure it could meet the heightened demands of the AI era. To meet this goal, the company focused on the CAS-to-CAS delay for reads (tCCDR) operation—the minimum time delay required for memory to read data consecutively from cells in different ranks³. In particular, SK hynix aimed to secure an increased tCCDR margin. This margin allows for deviations in timing to ensure that data can be transmitted accurately, ultimately improving system reliability.

²Peripheral circuit: A logic circuit that is responsible for selecting and controlling the cells that store data.
³Rank: A collection of basic data transmission units sent to the CPU from the DRAM module. A rank typically refers to 64 bytes of data to be transferred to the CPU as a bundle.

For HBM3E, the issue was that it becomes increasingly difficult to secure the minimum margin required for reliable data transmission during high-speed operation. This means that conflicts can occur when reading data across ranks at high speed, leading to potential read failures and a reduction in operational reliability.

Tasked with reducing the peripheral circuit size and improving the tCCDR margin, SK hynix turned its attention to developing a pioneering new design scheme which would open the door to the next-generation HBM3E.

A New Design: Leaping Forward With the World’s First 6-Phase RDQS Scheme

SK hynix overcame scaling and data transmission limitations in HBM3E by introducing the 6-phase RDQS scheme

Although SK hynix implemented several new design schemes and features in HBM3E, the world-first application of the 6-phase RDQS scheme was particularly notable. For HBM3, SK hynix had used the 4-phase RDQS scheme but the company saw an opportunity to push technical boundaries once again for HBM3E. This would ultimately enable the company to expand the memory capacity and improve the reliability of HBM3E.

Before looking at the advancements of the 6-phase RDQS scheme, it is prudent to consider the scheme’s role in HBM. The RDQS scheme is a circuit that produces the RDQS signals required for transmitting data from the HBM’s core dies, which contain the cells, to the base die, which contains the peripheral circuit. Overall, the RDQS scheme aims to minimize data skew⁴ from different ranks to avoid read failures.

⁴Data skew: The uneven distribution of data across different partitions in large-scale data processing. This can result in longer processing times as some partitions are required to handle more data than others.

Schematic diagrams showing the structural differences between the 4-phase and 6-phase RDQS schemes (upper diagrams) and a comparison of the schemes’ tCCDR margin (lower diagrams) (Source: Jinhyung Lee et al., High-Density Memories and High-Speed Interfaces, ISSCC 2024)

So how did the introduction of the 6-phase RDQS scheme reduce the size of the peripheral circuit? In the 4-phase RDQS scheme, multiple sets of FIFO-out data strobes⁵ (FDQS) and RDQS TSVs are required which inevitably leads to an increase of the peripheral area. The introduction of the 6-phase RDQS scheme can reduce the area of the peripheral circuit by cutting the number of FDQS and RDQS TSVs in half. This reduction of TSV signals means that the number of signals going back and forth between ranks is reduced, which can reduce the peripheral height.

⁵FIFO: A data structure that holds elements in the order they are received and provides access to those elements using a first-in, first-out basis.

Furthermore, the 6-phase RDQS scheme improved the tCCDR margin during the high-speed operation of HBM3E. This was realized as there is enough space between signals in the new scheme, so there is more margin for data transmission across ranks, or tCCDR operation. By securing this larger margin, the system becomes more tolerant of any deviations in timing, reducing the likelihood of read failures and therefore increasing system reliability.

Power in a Small Package: 6-phase RDQS Scheme Unlocks HBM3E

The application of the 6-phase RDQS scheme enabled HBM3E to maintain the same packaging size as HBM3 while offering improved density

The application of the 6-phase RDQS scheme contributed to the significant advancements in HBM3E’s key characteristics. First, the scheme enabled the reduction of the peripheral circuit height in the base die by 31%. Crucially, this reduction in the peripheral circuit height helped ensure that HBM3E has the same packaging size as HBM3 while offering an increased capacity from 16 Gb to 24 Gb.

In addition, the increased tCCDR margin stabilized the data transmission characteristics, which contributed to the enhancement in HBM3E’s data processing speed compared to its predecessor. While the 8-layer HBM3 can process up to 819 GB of data per second, the 8-layer HBM3E offers industry-leading data processing speeds of 1.18 terabytes (TB) per second. This rapid processing speed coupled with its vast capacity ensures HBM3E is optimized to meet the requirements of today’s AI applications.

Rulebreaker Interview: Youngjun Ku, Leading HBM Design

To find out more about the rulebreaking approach which led to the application of the 6-phase RDQS scheme to HBM3E, the SK hynix newsroom interviewed Technical Leader (TL) Youngjun Ku of Leading HBM Design. Ku discussed the significance of the new design scheme, as well as the challenges faced during the application process.

What were the main challenges when applying the 6-phase RDQS scheme to HBM3E?

“The 6-phase RDQS scheme significantly increases the overall design difficulty due to its complexity.

“The most straightforward way to address the issues with HBM3E was to improve transistor performance. However, when it seemed to reach certain limits with no room for further improvement, we resolved this by turning our attention to the design scheme, which was particularly challenging when working with HBM.

“As HBM products have a short gap between generations while realizing huge leaps in performance, the circuits require multiple changes. However, we tackled any problems through collaboration with numerous departments within the DRAM Design division.”

Why is the 6-phase RDQS scheme significant for HBM?

“To meet the demands of the AI era, HBM products need to increase their data processing speed. This requires stable data transmission by securing HBM’s timing margin. Therefore, schemes such as 6-phase RDQS, which help secure data transmission characteristics through TSV between the base and core die, will be essential in the age of AI.

“We believe that collaboration with our customers and the foundry industry will become even more important in the future as HBM products advance with the development of HBM4 and HBM4E, which double the data bandwidth and customized requirements. To maintain our leadership, we need to design products appropriate to our customers’ needs.”

How did your team’s rulebreaking approach ensure the development of the 6-phase RDQS scheme?

“When designing HBM products, there are a lot of challenges. The members of Leading HBM Design were constantly brainstorming to find solutions to these problems. Rather than fearing changes to the circuit design, we achieved great results by trusting in our ability to overcome challenges.”

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

The post [Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights first appeared on SK hynix Newsroom.

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

user — Tue, 10 Sep 2024 06:00:27 +0000

Challenging convention, defying limits, and aiming for the skies, rulebreakers remake the rules in their quest to come up with groundbreaking solutions to problems. Following on from SK hynix’s “Who Are the Rulebreakers?” brand film, this series showcases the company’s various “rulebreaking” innovations that have reshaped technology and redefined new industry standards. This second episode covers the adoption of HKMG technology for mobile DRAM.

What fuels progress in the rapidly changing semiconductor world? While invention is the driver behind many advancements, reimagining the use of existing technologies for new applications can also overcome barriers to progress. This latter approach enabled SK hynix to make huge strides in the mobile DRAM field.

While the semiconductor industry struggled to continue mobile DRAM scaling¹, SK hynix made a significant breakthrough with the world’s first application of High-K Metal Gate (HKMG) to mobile DRAM. Through this innovative use of the long-established HKMG process, the company was able to develop next-generation LPDDR² products which set new standards in performance.

¹Scaling: The reduction in size of semiconductors to produce better device performance, power efficiency, and cost.
²Low Power Double Data Rate (LPDDR): Low-power DRAM products for mobile devices, including smartphones and tablets, aimed at minimizing power consumption and featuring low voltage operation.

This Rulebreakers’ Revolutions episode focuses on SK hynix’s groundbreaking application of HKMG and the challenges the company overcame to integrate this process to mobile DRAM.

The Mission: Tackle Power Loss Issues to Continue Mobile DRAM Scaling

The growth of on-device AI and other applications is placing ever-increasing performance demands on mobile devices. In turn, mobile DRAM must continue scaling down and provide faster processing speeds to support these applications while maintaining low-power consumption. However, there are issues with the continued miniaturization of mobile DRAM transistors through traditional processes.

A DRAM typically includes cell transistors which store data and peripheral (peri.) transistors responsible for data input and output. To improve DRAM performance, it is necessary to scale down transistors which brings the source³ and drain⁴ closer together and increases the current. However, to reduce power consumption, the operating voltage to the gate⁵ must be decreased. Consequently, the gate insulating film must be thinned to improve transistor performance at a lower voltage.

In standard DRAM products including mobile DRAMs, this insulating film is generally made from silicon oxynitride (SiON) which encounters reliability issues when reduced in thickness. Moreover, the thinning of SiON insulators increases the amount of leakage current⁶, leading to a loss of power. This is a significant issue for battery-powered mobile devices in which low-power consumption is critical to extend the usage time on a single charge.

³Source: The terminal through which the majority charge carriers enter the transistor.
⁴Drain: The terminal through which the majority charge carriers exit from the transistor.
⁵Gate: A component in a transistor that controls the flow of electric current by acting as an on-off switch.
⁶Leakage current: Unwanted flow of electrical current that occurs when the transistor is in the off state.

SiON insulators in conventional transistors are a barrier to DRAM scaling

To tackle this power consumption issue and ultimately ensure the continued scaling of mobile DRAM without compromising performance, SK hynix once again broke the rules of convention and turned to a long-standing technology—HKMG.

The Future Lies in The Past: World-First HKMG Application & Integration Challenges

HKMG was commercialized over a decade ago, first used in logic semiconductors and then applied to high-performance DRAM memory. Although HKMG was an established technology, SK hynix was the first company to see it as a solution to the scaling limitations of mobile DRAM while others continued with traditional processes. This pioneering application of HKMG and optimization of the process revolutionized the mobile DRAM sector, paving the way for ultra-low-power and ultra-high-speed solutions.

The groundbreaking application of HKMG enabled mobile DRAM to continue scaling

So what is HKMG and how does it solve the issues of the traditional SiON process? The HKMG process involves replacing the traditional SiON insulator in transistors with a thin High-K film which prevents leakage currents and improves reliability. Offering high levels of permittivity⁷, High-K film provides equivalent electrical characteristics as a film five times thicker. This thinner film enables continuous transistor scaling, resulting in faster speeds and lower power characteristics compared to SiON-based transistors.

⁷Permittivity: Degree of how many electrons can be stored inside a gate.

The HKMG process tackled the power and performance issues associated with SiON insulators in conventional transistors

As the whole HKMG process had never been applied to mobile DRAM before, SK hynix had to optimize the process and overcome challenges to ensure its smooth application. One of the most significant risks the company recognized was the potential for defects to arise from the application of HKMG to mobile DRAM. In particular, when applying the HKMG process to an LPDDR product for the first time, various stability issues arising from the use of new materials could cause chip defects. To combat this, SK hynix conducted preliminary evaluations through pilot products. Through these various evaluations and tests along with leveraging cross-company expertise, SK hynix was able to maximize transistor performance and ultimately secure the integrated process solution for mobile DRAM.

Unlocking New LPDDR Solutions

The first-ever mobile DRAM products made with the HKMG process offered huge leaps in power and speed

The successful integration of the HKMG process with mobile DRAM paved the way for SK hynix to develop new ultra-low-power and rapid LPDDR solutions. In November 2022, the company released the world’s first ever mobile DRAM with the integrated HKMG process, Low Power Double Data Rate 5X (LPDDR5X). The product offered ultra-low operating power of 1.01–1.12V and an operating speed of 8.5 Gbps. LPDDR5X is 33% faster and uses 21% less power compared to the previous generation, ensuring it meets both sustainability goals to lower carbon emissions and technological targets.

Just two months later, SK hynix once again set new standards in mobile DRAM with the introduction of Low Power Double Data Rate Turbo (LPDDR5T). While LPDDR5T operates at the same low voltage as LPDDR5X and provides a 21% reduction in power consumption from LPDDR5, it also offers significant leaps in speed from its predecessor. At the time of its release, LPDDR5T was the world’s fastest mobile DRAM, boasting an impressive operating speed of 9.6 Gbps—13% faster than LPDDR5X and 50% quicker than LPDDR5. Such speeds were only thought of as possible with the next-generation LPDDR6, but the company was able to reach new heights ahead of schedule thanks largely to the application of HKMG.

Rulebreaker Interview: Jongchan Choi, Product Solution Process Integration

To learn more about the “rulebreaking” approach which led to the application of HKMG to mobile DRAM, the SK hynix newsroom interviewed Team Leader Jongchan Choi of Product Solution Process Integration. Choi, who helped develop the process solution when HKMG was first applied to LPDDR products, discusses the future direction of HKMG and its potential future applications beyond mobile DRAM.

Can you tell us more about why HKMG was applied to mobile DRAM?

“In the AI era, the market demands mobile DRAM that not only offers low power but also high-speed characteristics. Generally, power and speed have a trade-off relationship, making it very difficult to improve both simultaneously. However, HKMG technology is a solution that can overcome this challenge.

“With the goal of regaining leadership in the mobile DRAM market and achieving the highest possible speed, we decided to apply HKMG technology to mobile DRAM through a thorough technological preparation process. I believe it provides a foundation for expanding into various DRAM applications that meet customer demands by significantly improving power leakage and speed.”

How do you foresee the evolution of HKMG and HKMG-based solutions?

“SK hynix continues to improve devices and processes to maximize the competitiveness of the first-generation HKMG Technology Platform. Additionally, as customer expectations for high speed and low power continue to rise, we must continue to develop technology which maximizes DRAM performance. In light of this, we are developing the next-generation HKMG Technology Platform.

“In terms of specific products, the LPDDR5 lineup has a growing array of applications including not only mobile devices but also data centers that require vast amounts of power. These ultra-low-power LPDDR solutions cut energy consumption, helping to reduce carbon emissions and thereby maximizing the ESG values that SK hynix pursues.”

What challenges did you face during the application of HKMG and how did SK hynix’s “rulebreaking” spirit help you overcome these obstacles?

“HKMG is a particularly challenging technology to implement and required thorough preparation to ensure its successful application. We determined that the existing technology pre-verification process was limited, so we significantly enhanced the HKMG verification procedures and executed a schedule and goals that were ‘challenging but achievable’ for us. This shows how we continually look to push the limits to reach new heights.

“Collaboration was also key to the success of the project. After the decision was made to deploy HKMG to overcome the limits of high speed and low power in mobile DRAM, the entire company organized teams and provided resources for technology development.

“I believe that by communicating the importance and value of HKMG, recognizing contributions to successful technology development, and rewarding achievements, we help motivate members to stay focused and not lose sight of our long-term development goals.”

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

The post [Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application first appeared on SK hynix Newsroom.

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

user — Tue, 30 Jul 2024 06:00:43 +0000

Challenging convention, defying limits, and aiming for the skies, rulebreakers remake the rules in their quest to come up with groundbreaking solutions to problems. Following on from SK hynix’s “Who Are the Rulebreakers?” brand film, this series showcases the company’s various “rulebreaking” innovations that have reshaped technology and redefined new industry standards. This first episode covers the development of MR-MUF for HBM.

Smaller. Faster. Higher bandwidth. Better performance. Today’s leading memory products are rapidly evolving to meet the intense demands of the AI era. However, these advancements bring with them a challenge which can hinder the development of next-generation products—excessive heat generation.

To tackle this issue, SK hynix made an unprecedented breakthrough by developing a new and innovative packaging technology called MR-MUF¹ that improves heat dissipation in chips. Applied to the company’s groundbreaking HBM² products since 2019, MR-MUF has set SK hynix aside from the competition. As the only company to use MR-MUF and having received excellent client evaluations for the heat dissipation characteristics of its HBM products which apply the technology, SK hynix has risen to the position of HBM market leader.

¹Mass reflow-molded underfill (MR-MUF): Mass reflow is a technology that connects chips together by melting the bumps between stacked chips. Molded underfill fills the gaps between stacked chips with protective material to increase durability and heat dissipation. Combining the reflow and molding process, MR-MUF attaches semiconductor chips to circuits and fills the space between chips and the bump gap with a material called liquid epoxy molding compound (EMC).
²High Bandwidth Memory (HBM): A high-value, high-performance product that possesses much higher data processing speeds compared to existing DRAMs by vertically connecting multiple DRAMs with through-silicon via (TSV).

This Rulebreakers’ Revolutions episode will look at how the pioneering development of MR-MUF, particularly its new materials with high thermal conductivity, solved the problem of excessive heat generation in next-generation HBM products.

The Mission: Overcome the Problem of Heat Generation

As memory products evolve, heat generation becomes an increasingly pressing issue for several reasons. For example, the miniaturization of semiconductors negatively impacts heat dissipation due to the reduced surface area and increased power density. In the case of stacked DRAM products such as HBM, thermal resistance increases due to the longer heat transfer paths, while thermal conductivity is limited by the materials between chips. Moreover, the continuous advancements in speed and capacity result in increased heat generation.

The inability to sufficiently control heat in semiconductor chips can negatively impact a product’s performance, lifecycle, and functionality. This can become a serious concern for customers and significantly impact factors including productivity, energy costs, and competitiveness. Consequently, heat dissipation, along with capacity and bandwidth, has become a key consideration during the development of advanced memory products.

Attention has therefore turned to semiconductor packaging technology as one of its main functions is heat control. Up until the second generation of HBM, HBM2, SK hynix applied the industry-standard TC-NCF³ process to its HBM products. However, with advancements in HBM that required chips to become thinner to accommodate additional chip layers, the applied packaging technology needed to control higher levels of heat and pressure. Issues such as chip warpage due to pressure and thickness limitations in densely stacked products also needed to be addressed as SK hynix planned to develop its next-generation products. At this point, the company needed to think outside the box by developing a new packaging technology for its future products.

³Thermal compression non-conductive film (TC-NCF): A method of stacking chips by applying a film-like substance between chips. Heat and pressure are applied to melt the substance so chips are glued together.

MR-MUF & Its New Materials: The Missing Pieces to the Heat Control Puzzle

As SK hynix was developing HBM2E, the third generation of HBM, controlling heat became a major focal point for improvement. Even when TC-NCF was being recognized as a packaging solution suitable for densely stacked products, SK hynix challenged the status quo and strove to develop a new packaging technology offering improved heat dissipation. After countless tests and trials, the company unveiled its new packaging technology MR-MUF in 2019 which would change the future of the HBM market.

The structural difference between TC-NCF and MR-MUF that influence heat dissipation

Developed by multiple teams at SK hynix, MR-MUF heats and interconnects all the vertically stacked chips in HBM products at once. This makes it more efficient than TC-NCF which applies a film-type material after each chip is stacked. Moreover, MR-MUF increases the number of thermal dummy bumps—which are effective at dispersing heat—by up to four times compared to TC-NCF.

Another important feature of MR-MUF is the addition of a protective material called EMC⁴ used to fill the spaces between chips. A thermosetting polymer with excellent mechanical and electrical insulation as well as heat resistance, EMC addressed the need for high environmental reliability and control over chip warpage. Due to the application of MR-MUF, HBM2E improved heat dissipation performance by 36% compared to its predecessor, HBM2.

⁴Epoxy molding compound (EMC): A heat dissipation material based on epoxy resin, a type of thermosetting polymer, that seals semiconductor chips to protect them from environmental factors such as heat, moisture, and shock.

Although MR-MUF was also used for HBM2E’s successor, the 8-layer HBM3, SK hynix elevated the MR-MUF process to another level when developing the 12-layer HBM3 in 2023. As the DRAM chips had to be 40% thinner than the chips used in the 8-layer HBM3 in order to maintain the product’s overall thickness, chip warpage became a significant issue. SK hynix actively responded by developing Advanced MR-MUF, introducing the industry’s first chip control technology⁵ and new protective materials that improved heat dissipation. In this process, SK hynix once again achieved innovation in materials as the new EMC applied in Advanced MR-MUF offered a 1.6-time improvement in heat dissipation properties compared to the EMC for the original MR-MUF.

⁵Chip control technology: The application of a momentary burst of high heat to each chip as it is stacked, causing the bump under the top chip to fuse to a thin pad on top of the bottom chip. The pad holds the chip together and protects it from warpage.

With Heat Control, SK hynix Mass-Produces Highest Level of HBM

A timeline of HBM’s multiple generations and progress in heat dissipation

Starting with the development of HBM2E, the application of MR-MUF and the subsequent Advanced MR-MUF enabled SK hynix to produce the industry’s highest standards of HBM products. Fast-forward to 2024, SK hynix became the first company to mass-produce HBM3E, the latest HBM product which boasts the highest standards of performance. HBM3E saw a 10% improvement in heat-dissipation performance compared with its previous generation, the 8-layer HBM3, following the application of Advanced MR-MUF to become the in-demand memory product in the AI era. Looking ahead, the company is set to maintain its HBM leadership as it has announced plans to bring forward the mass production of the next-generation HBM4 to 2025.

Rulebreaker Interview: Kyoung-Moo Harr, HBM Package Product

To find out more about the original approach which led to the development of MR-MUF and advancement of HBM, the SK hynix newsroom spoke with Technical Leader Kyoung-moo Harr of HBM Package Product. Having actively supported the development of MR-MUF through exploration, testing, and verification of new materials, Harr discusses the impact of this innovative process.

How significant was the successful development of HBM products with MR-MUF for SK hynix? What are the major breakthroughs of MR-MUF and Advanced MR-MUF in terms of material innovation?

“MR-MUF has propelled us to the top of the HBM market and enabled us to secure HBM leadership. Ever since we made the calculated risk of applying MR-MUF to HBM2E rather than TC-NCF like other companies in the industry, SK hynix has been outpacing its competitors. Enabling the mass production of unprecedented HBM products with increasingly more layers, MR-MUF is a true testament to the company’s persistent pursuit of innovation.

“In terms of material innovation, MR-MUF features EMC which has stronger heat dissipation qualities than NCF. This played a key role in improving the heat control capability of MR-MUF and enhancing the environmental reliability compared to TC-NCF. For Advanced-MUF, SK hynix took its EMC a step further by creating a new version with improved heat dissipation properties.”

What are some behind-the-scenes efforts during the development of MR-MUF that you would like to highlight?

“Behind these highly advanced technologies lies a continuous cycle of tests and evaluations for verifying and enhancing the qualities of new materials that would be used in the packaging process.

“When developing Advanced MR-MUF, it was crucial that the new EMC was continuously applied to a universal test vehicle⁶ (UTV) for reliability testing. A UTV with the same specifications of a HBM product undergoes WLP⁷ to become a sample. It then proceeds to a look ahead reliability⁸ (LAR) test to identify defects. Only materials that pass the test and receive necessary improvements are applied to the final HBM products.”

⁶Universal test vehicle (UTV): Samples produced in a product’s early development stage to test and establish its specifications and standards.
⁷Wafer-level package (WLP): Technology that produces end products by packaging and testing a wafer all at once before the wafer is diced. It differs from the conventional packaging method of processing a wafer and dicing each chip.
⁸Look ahead reliability (LAR): A preliminary test before quality evaluation that seeks to set countermeasures for defections found during the test. These countermeasures need to be applied during quality assessment to fix defects.

How did SK hynix’s rulebreaker spirit encourage employees to break convention with the development of MR-MUF?

“Our company has a “rulebreaking” culture of encouraging everyone to choose challenging goals instead of settling for easier ones. In addition, all members no matter their department are committed to one-team collaboration and strive to be the best role players they can possibly be for the team.

“This was clear during the development of MR-MUF, when members from various departments collaborated on the project to ensure its success. It truly was a company-wide effort as members came together to make this innovation possible. My role also involved significant collaboration as I supported engineers in their development of the process. This was on top of my main duties of conducting preliminary risk evaluations of materials, drawing up technical verification plans, monitoring competitors, and identifying customer needs ahead of time.

“At SK hynix, we are all rulebreakers because we believe our joint efforts allow us to reach previously unimaginable heights.”

[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

The post [Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights first appeared on SK hynix Newsroom.

[Brand Video] Who Are the Rulebreakers?

user — Mon, 30 Oct 2023 06:00:50 +0000

Galileo. Picasso. The Wright Brothers. Throughout history, innovation in everything from astronomy and art to technology, engineering and beyond has been brought about by rulebreakers. At a time when the semiconductor industry is facing challenges to continue technological advancements, it is more important than ever to break from the status quo and take a different approach. By breaking the rules and pushing technological boundaries, SK hynix is able to develop groundbreaking memory solutions which help create unforgettable experiences for people around the world. Find out more about why SK hynix breaks the rules in the first of a series of brand videos below.

The post [Brand Video] Who Are the Rulebreakers? first appeared on SK hynix Newsroom.