What fuels progress in the rapidly changing semiconductor world? While invention is the driver behind many advancements, reimagining the use of existing technologies for new applications can also overcome barriers to progress. This latter approach enabled SK hynix to make huge strides in the mobile DRAM field.

While the semiconductor industry struggled to continue mobile DRAM scaling¹, SK hynix made a significant breakthrough with the world’s first application of High-K Metal Gate (HKMG) to mobile DRAM. Through this innovative use of the long-established HKMG process, the company was able to develop next-generation LPDDR² products which set new standards in performance.

¹Scaling: The reduction in size of semiconductors to produce better device performance, power efficiency, and cost.
²Low Power Double Data Rate (LPDDR): Low-power DRAM products for mobile devices, including smartphones and tablets, aimed at minimizing power consumption and featuring low voltage operation.

This Rulebreakers’ Revolutions episode focuses on SK hynix’s groundbreaking application of HKMG and the challenges the company overcame to integrate this process to mobile DRAM.

The Mission: Tackle Power Loss Issues to Continue Mobile DRAM Scaling

The growth of on-device AI and other applications is placing ever-increasing performance demands on mobile devices. In turn, mobile DRAM must continue scaling down and provide faster processing speeds to support these applications while maintaining low-power consumption. However, there are issues with the continued miniaturization of mobile DRAM transistors through traditional processes.

A DRAM typically includes cell transistors which store data and peripheral (peri.) transistors responsible for data input and output. To improve DRAM performance, it is necessary to scale down transistors which brings the source³ and drain⁴ closer together and increases the current. However, to reduce power consumption, the operating voltage to the gate⁵ must be decreased. Consequently, the gate insulating film must be thinned to improve transistor performance at a lower voltage.

In standard DRAM products including mobile DRAMs, this insulating film is generally made from silicon oxynitride (SiON) which encounters reliability issues when reduced in thickness. Moreover, the thinning of SiON insulators increases the amount of leakage current⁶, leading to a loss of power. This is a significant issue for battery-powered mobile devices in which low-power consumption is critical to extend the usage time on a single charge.

³Source: The terminal through which the majority charge carriers enter the transistor.
⁴Drain: The terminal through which the majority charge carriers exit from the transistor.
⁵Gate: A component in a transistor that controls the flow of electric current by acting as an on-off switch.
⁶Leakage current: Unwanted flow of electrical current that occurs when the transistor is in the off state.

SiON insulators in conventional transistors are a barrier to DRAM scaling

To tackle this power consumption issue and ultimately ensure the continued scaling of mobile DRAM without compromising performance, SK hynix once again broke the rules of convention and turned to a long-standing technology—HKMG.

The Future Lies in The Past: World-First HKMG Application & Integration Challenges

HKMG was commercialized over a decade ago, first used in logic semiconductors and then applied to high-performance DRAM memory. Although HKMG was an established technology, SK hynix was the first company to see it as a solution to the scaling limitations of mobile DRAM while others continued with traditional processes. This pioneering application of HKMG and optimization of the process revolutionized the mobile DRAM sector, paving the way for ultra-low-power and ultra-high-speed solutions.

The groundbreaking application of HKMG enabled mobile DRAM to continue scaling

So what is HKMG and how does it solve the issues of the traditional SiON process? The HKMG process involves replacing the traditional SiON insulator in transistors with a thin High-K film which prevents leakage currents and improves reliability. Offering high levels of permittivity⁷, High-K film provides equivalent electrical characteristics as a film five times thicker. This thinner film enables continuous transistor scaling, resulting in faster speeds and lower power characteristics compared to SiON-based transistors.

⁷Permittivity: Degree of how many electrons can be stored inside a gate.

The HKMG process tackled the power and performance issues associated with SiON insulators in conventional transistors

As the whole HKMG process had never been applied to mobile DRAM before, SK hynix had to optimize the process and overcome challenges to ensure its smooth application. One of the most significant risks the company recognized was the potential for defects to arise from the application of HKMG to mobile DRAM. In particular, when applying the HKMG process to an LPDDR product for the first time, various stability issues arising from the use of new materials could cause chip defects. To combat this, SK hynix conducted preliminary evaluations through pilot products. Through these various evaluations and tests along with leveraging cross-company expertise, SK hynix was able to maximize transistor performance and ultimately secure the integrated process solution for mobile DRAM.

Unlocking New LPDDR Solutions

The first-ever mobile DRAM products made with the HKMG process offered huge leaps in power and speed

The successful integration of the HKMG process with mobile DRAM paved the way for SK hynix to develop new ultra-low-power and rapid LPDDR solutions. In November 2022, the company released the world’s first ever mobile DRAM with the integrated HKMG process, Low Power Double Data Rate 5X (LPDDR5X). The product offered ultra-low operating power of 1.01–1.12V and an operating speed of 8.5 Gbps. LPDDR5X is 33% faster and uses 21% less power compared to the previous generation, ensuring it meets both sustainability goals to lower carbon emissions and technological targets.

Just two months later, SK hynix once again set new standards in mobile DRAM with the introduction of Low Power Double Data Rate Turbo (LPDDR5T). While LPDDR5T operates at the same low voltage as LPDDR5X and provides a 21% reduction in power consumption from LPDDR5, it also offers significant leaps in speed from its predecessor. At the time of its release, LPDDR5T was the world’s fastest mobile DRAM, boasting an impressive operating speed of 9.6 Gbps—13% faster than LPDDR5X and 50% quicker than LPDDR5. Such speeds were only thought of as possible with the next-generation LPDDR6, but the company was able to reach new heights ahead of schedule thanks largely to the application of HKMG.

Rulebreaker Interview: Jongchan Choi, Product Solution Process Integration

To learn more about the “rulebreaking” approach which led to the application of HKMG to mobile DRAM, the SK hynix newsroom interviewed Team Leader Jongchan Choi of Product Solution Process Integration. Choi, who helped develop the process solution when HKMG was first applied to LPDDR products, discusses the future direction of HKMG and its potential future applications beyond mobile DRAM.

<Other articles from this series>

[Rulebreakers’ Revolutions] How MR-MUF’s Heat Control Breakthrough Elevated HBM to New Heights

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

The post [Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application first appeared on SK hynix Newsroom.

¹Self-aligned fabrication: A patterning method using a spacer and a hardmask to create a smaller pattern that cannot be created with the wavelength of conventional UV. During a form of multi-patterning called self-aligned double patterning (SADP), the spacer is self-aligned with the hardmask in a subsequent step to double the number of patterns. For self-aligned quadruple patterning (SAQP), another round of SADP is performed to quadruple the number of patterns.

Selective Deposition of Thin Films Through AS-ALD

AS-ALD is a bottom-up fabrication process in which thin film materials are chemically deposited onto selective areas of a large wafer’s surface while controlling uniformity, conformality, and thickness at the angstrom² level. The area covered with thin films is known as a growth area, while the area where no chemical reaction occurs during AS-ALD is called a non-growth area. The efficacy of AS-ALD is strongly influenced by precursor design, as it relies on the combination of precursor³ reactivity and strategically-sized molecules to block different precursors. It offers advantages over current self-aligned fabrication schemes by reducing the number of lithography processes and the use of toxic reagents in the patterning process to produce memory devices. This helps to not only reduce edge placement errors (EPEs) but also lower manufacturing costs. Ultimately, AS-ALD enables bottom-up and self-aligned deposition with respect to the underlying device layers. This has been proven to be a huge advancement from ALD that typically leads to uniform deposition on the entire surface without any control of the lateral arrangement of the atoms. Thus, AS-ALD provides much more precision and efficiency in this process.

²Angstrom: A unit of length used to measure the distance between atoms, equal to 10^-10meters.
³Precursor: High-purity gas or liquid materials used in key steps during the manufacturing of semiconductor devices. The precursor material not only sticks to various surfaces, but it also allows only one atomic layer to be produced per ALD cycle.

Figure 1. An overview of the AS-ALD process (Source: Parsons et al., Chemistry of Materials)

Understanding ALD Technology

Before exploring AS-ALD in detail, it is important to first understand the basics of ALD, a deposition technique that has become widely used in the semiconductor industry over the past few decades. During ALD, the raw materials of films—precursors and reactants—are alternately exposed to the substrate surface during multiple cycles to build up ultra-thin film layers of atomic thickness. This process highlights the importance of ALD’s self-limiting surface reaction characteristic for AS-ALD. Since a new precursor cannot react where another precursor has previously reacted, ALD can control the thickness of the thin film at the atomic level by limiting subsequent molecular adsorption⁴. In other words, when the surface reaction is properly adjusted, a precursor adsorption reaction can be achieved in a desired region and a precursor desorption reaction can occur in another region. This can be considered the inherent growth characteristic of ALD.

⁴Adsorption: The adhesion of atoms, ions, or molecules from a gas, liquid, or dissolved solid (adsorbate) to a solid surface (adsorbent).

Figure 2. The ALD cycle

As an example, Al₂O₃, or aluminum oxide, films that are deposited by ALD processes using water exhibit different nucleation and growth behaviors depending on both the aluminum precursor and the substrate at a given process temperature. As shown in the comparison of aluminum precursors in Figure 3, the surface reaction and coverage rates are determined by the magnitude of the reaction between specific precursors and Lewis acids and bases⁵. This suggests the importance of selecting an appropriate precursor for ALD processes.

⁵Lewis acids and bases: Described by the Lewis theory of acid-base reactions as an electron-pair acceptor and electron pair donors, respectively. Therefore, a Lewis base can donate a pair of electrons to a Lewis acid to form a product containing a coordinate covalent bond.

Figure 3. The growth per cycle in relation to precursor exposure

Precursor Selection Key for AS-ALD

Precursor selection and design is much more critical in the AS-ALD process compared to ALD as selective growth may be achieved during one ALD process but fail in another. This is due to ALD not being able to control the area where the precursor contacts the substrate. Metal alkyl⁶ precursors such as trimethylaluminum (TMA) and diethylzinc (DEZ) are the most widely used precursors for ALD due to their high vapor pressure that allows them to be efficiently delivered to the deposition reactor. Consequently, a wide range of precursors including alkyls, halides, amidinates, cyclopentadienyls, β-diketonates, alkoxides, and heteroleptic precursor systems have been studied to see whether they are also adequate for AS-ALD. These precursors were found to be highly reactive, so they provide a strong thermodynamic favorability that leads to adsorption on the surface. Therefore, to control the surface reaction of not only ALD but also AS-ALD, inhibition layers such as self-assembled monolayers (SAMs) or small molecule inhibitors (SMIs) are used to block adsorption in most studies about the precursors of Al₂O₃ and ZnO (zinc oxide). However, TMA precursors are known to be the most difficult to use in AS-ALD. As there is a loss of selectivity with SAMs, TMA precursors experience adsorption to the SAMs after tens of cycles. In terms of growth inhibition, DEZ is more suitable than TMA as a precursor because the blocking selectivity of TMA only goes up to 6 nanometers (nm), while that of DEZ is at least 30 nm on the same SAM surface.

⁶Metal alkyl: Coordination complexes that contain a bond between a transition metal and an alkyl ligand.

To get a better grasp of these concepts, it is prudent to become familiar with AS-ALD’s mechanisms that are based on the characteristics of precursors. Past studies have compared a series of precursors that have the same central metal atom but different ligands⁷ to determine how key precursor design parameters affect the efficacy of AS-ALD. By changing the number of methyl and chloride groups in the Al(CH₃)_xCl_3-x (x = 0, 2, 3) precursor and the chain length of the alkyl ligand in the AIC_yH_2y+1 (y = 1, 2) precursor, the impact of precursor chemistry on selectivity can be explained. For example, the SAM-terminated substrate that serves as the non-growth surface is significantly different from a silicon substrate. As the application of SAMs on the silicon surface would be flawed, precursor molecules can penetrate the SAM structure where Lewis acidic SiO_x attracts molecule adsorption. The chloride precursors adsorbed on a silicon substrate with native oxides have a higher Lewis acidity compared to the alkyl precursors. Thus, the precursors containing chlorines require a much longer purge time⁸ on the SAM. However, this adsorption of chloride precursors is mainly caused by physisorption as the activation energy for the chemical reaction with SAMs and/or the SiO_x surface is relatively high. In other words, although an extended purge time is required, it is possible to remove the adsorbed chloride-precursor molecules from SAMs. In contrast, alkyl precursors are hardly eliminated during the chemical reaction.

⁷Ligand: Nonmetal atoms or groups of atoms that surround a central metal atom.
⁸Purge time: The time it takes to remove excessive residue.

Regarding the size of molecules, ALD of Al₂O₃ using the Al(C₂H₅)₃, or triethylaluminum (TEA), precursor is most effectively blocked by a SAM inhibitor under optimal conditions. Conversely, the widely used TMA precursor is least effectively blocked among the tested precursors. Also, there is a significant difference in the energy of dimer⁹ formation, or dimerization, among the aluminum precursors. Only up to 1% of the AlCl₃ and Al(CH₃)₂Cl precursors exist as dimers at 200 °C, whereas 99% of the Al(CH₃)₃ and Al(C₂H₅)₃ precursors remain as monomers, which causes a difference in the average size of molecules. Through such observations, it is clear that the size of the precursor, which is governed by dimerization energy, is the most important factor in raising the selectivity of AS-ALD. In other words, the combination of precursor reactivity and the size of the effective molecules affects the blocking of different precursors. This is the reason Al(C₂H₅)₃, which has a low Lewis acidity but a relatively large size, provides optimal blocking.

⁹Dimer: A substance made from the polymerization of two identical or similar molecules, which are generally hydrogen.

Figure 4. Selectivity in relation to the thickness of precursors and reactants (Source: Oh et al., Chemistry of Materials)

Main Challenges for Precursor Development in AS-ALD

The issue with all of the approaches developed for AS-ALD is that growth occurs even on surfaces where deposition was not required. This poses a problem for semiconductor manufacturers which require perfectly selective films that are only a few nanometers thick. Therefore, rather than focusing on the pattern itself during self-aligned fabrication, more attention should be placed on the fact that deposition must only occur with practical applications on 3D device structures.

The precursors that have been developed to date are designed for ALD processes to effectively form films. However, in the case of AS-ALD, thin films must not only grow in specific areas just as in conventional ALD, but their growth must be completely or partially blocked in other areas as well. In other words, the process window is extremely narrow as the adsorption and desorption of molecules occur within the same process. Ultimately, there needs to be development in new precursors that will be able to widen this process window.

The Quest for Next-Generation AS-ALD

The field of nanoscale device fabrication is witnessing a paradigm shift that is driven by the innovative approach of AS-ALD. As the semiconductor industry grapples with the challenges of IC scaling, AS-ALD has emerged as a promising solution that not only reduces edge placement errors but also slashes manufacturing costs. During this process, the precise selection of precursors is an intricate and vital task that requires a deep understanding of the surface chemistry and the characteristics of these materials. As this technology enables deposition to occur solely in specified areas which are often just a few nanometers thick, the full potential of AS-ALD lies within factors such as novel precursor designs and widening the narrow process window. If AS-ALD can realize these developments, it is set to play a key role in realizing smaller, more precise, and higher quality semiconductor products.

The post Enabling Nanoscale Device Fabrication Through Area-Selective Atomic Layer Deposition first appeared on SK hynix Newsroom.

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It’s very challenging to further miniaturize components that are already only a few nanometers wide.

The history of electronics is a study in the progression and evolution of miniaturization, as electrical systems matured and migrated to become what we now consider electronics. The reason older tech is huge is that it was full of individual components that were literally wired together. All of the electronics processes that we do today, with digitally driven solid-state devices, had to be done in a brute-force analog manner.

In the case of the transistors that make up our modern microcontrollers and processors, the antique analog versions were called vacuum tubes [1], variations on light bulb technology originally discovered in 1880 by Thomas Edison. Exited metal plates between filament grids in the vacuum-sealed glass bulbs regulated the passage of current but were very power inefficient (because they were modified light bulbs) and very fragile (also because they were modified light bulbs).

Figure 1. Circuit diagram of the Edison discovery.

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These issues of power and size in electronics were such a fundamental aspect of early electronics that it shaped both popular and professional history. The first computers and their rows upon rows of vacuum-tube-filled racks engulfed a large room and gave off so much heat that the first computer bug reported was an actual insect attracted to the tubes [2]. Even in science fiction, an art designed to inspire futuristic thought, most authors predicted powerful computers—none predicted small pocket-sized smart devices.

Kilby, Noyce, and the Birth of the Chip

The discovery of the semiconductor and the creation of solid-state transistors in the 1960’s began the evolutionary process in electronics [3], laying the foundation for the world we have today. Instead of using a brute-force approach of wires and grids in a vacuum tube, a semiconductor device works by controlling the passage of electrons through a solid monocrystalline piece of semiconducting material. (There is an entirely different revolution going on in semiconductor materials, which we’ll touch on later.)

These semiconductor devices, even in their first iterations, were significantly smaller, lighter, better performing, cooler operating, and much more efficient than their glass-based forefathers. The breakthrough in semiconductors enabled the creation of the integrated circuit (IC), although there were several important technology hurdles that had to be overcome. These included the actual forming of devices in the crystal, the need to electrically isolate components, and the creation of electrical connections within the IC.

The birth of the IC is a story in parallel development. Jack Kilby, a radio engineer and World War II veteran, made the first hybrid IC in May 1958 from germanium [4], followed closely in January of 1959 by Robert Noyce, who unveiled his design of a planar integrated circuit [5]. Since then, semiconductor devices have been continuously miniaturizing.

Later on, in the early 70’s, IC feature device size (the space between the components and connection vias) decreased to 10 μm, and the number of the MOSFETs in a chip exceeded 1,000 [6]. In modern days, chips have gone down to 7nm spacing, with 5nm planned, and work underway for 2nm and less.

I/O, Logic, and Power

There are many aspects that need to be addressed when making electronics smaller in general, including the integration and management of the data input/output (I/O), the logic IC itself, and the power needed to drive it all. The demands of each create a juggling act the electronic designer must perform when creating products.

At the circuit-board level, miniaturization involves high levels of component integration. For example, a product could require an inertial sensor, a compass, temperature and presence sensors, as well as those for images and light. An integrated sensor module groups sensors based on related technologies into a single package, saving significant space.

Meanwhile, package-level miniaturization forces include the shrinking of power electronics due to the advent of new wide-bandgap semiconductors. These new materials, Gallium Nitride (GaN) and Silicon Carbide (SIC) are enabling a 60%+ reduction in the size of power supplies while also increasing performance by up to 300% [7]. They are enabling significant reduction in products simply by making the power electronics smaller.

We must consider the circuit-level miniaturization process as well, which relies on simplifying and/or optimizing the system. This approach leverages advances in device integration and the new power electronics, which enable advanced circuits with smaller passive devices and significantly smaller footprints. It can be leveraged with next-generation user interfaces that eliminate the need for a keypad or other space-hungry input method.

When it comes to logic devices, all issues at the macro-level must also be addressed at the chip level. How many devices can be integrated on a chip? How closely can the components of a chip be put together before they start interfering with one another? How do you get power in the right amount (current) and level (voltage) to the parts of the chip that need it?

Shrinking the Chip

There are several limiting factors when it comes to miniaturization. The first limit is defined by basic physics, in this case the distance of atoms in the material. It’s literally impossible to make the device structures less than the atomic distance, which does define a true lower limit to nano-electronics. This lower limit isn’t the real final barrier to miniaturization, however, as there is a fundamental limit defined by the distance the electrons can tunnel in the material.

The smaller chips get, the harder it is to control aspects like the leakage current between the source and drain of the transistors involved. This is regarded as one of the main limits to miniaturization, because it’s impossible to suppress the diffusion of electrons from the source to the channel at normal temperatures.

Still, the industry will continue to shrink electronic devices of all types because they are critical to so many aspects of our future smart Cloud-enabled Internet of Things (IoT)-oriented society. Both at the macro-level and the micro-level, expect to see higher levels of component integration, both planar and 3D, as well as further advances in materials for both the chips and their interconnects.

In the sense of vertical integration, SK hynix’s 176-layer 512 Gigabit (Gb) Triple-Level Cell (TLC) 4D NAND flash is a good example of the current state of the art [8]. The third generation 4D product that allows the bit productivity to be improved by 35% and the read speed increased by 20% over legacy devices. The data transfer speed also has been improved by 33% to 1.6Gbps without increasing the number of processes.

Figure 2. SK hynix’s 176-layer 512 Gb TLC 4D NAND Flash

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In regard to material advancements, just as piezoelectric semiconductors like Gallium Nitride have revolutionized the power electronics industry, they offer the promise to do the same for logic chips. One of the major benefits of a piezoelectric semiconductor is its ability to switch at extremely high speeds. Currently advanced GaN power devices can switch up to 40 MHz [9], and if these materials can be adapted to logic circuits, could enable a jump of several orders of magnitude in processor performance at the same feature size.

Another area of approach to miniaturize chips is to improve the way we flash the mask pattern onto the wafer itself. The more we can improve pattern resolution, the closer we can get to the theoretical limits in smaller sizes. The latest lithography methods [10] use short wavelengths in the blue or ultraviolet range.

Figure 3. A diagram of EUV equipment

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For instance, in the semiconductor memory industry SK hynix recently announced the mass production of its cutting-edge 1anm 8Gb LPDDR4 DRAM by using EUV equipment [11]. As one of the first to successfully implement the technology in mass production, several other major manufacturers are expected to follow in SK hynix’s footsteps as confidence grows in the application of EUV.

Figure 4. SK hynix’s 1anm 8Gb LPDDR4 DRAM Using EUV Equipment

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Integration is key

Another aspect of design where the micro mimics the macro is in the integration of functionality. Just as a product can be made smaller by integrating various devices on the circuit board, the circuit itself can be made smaller by integrating function blocks into the chip.

By providing functions that used to require their own device, highly integrated chips enable a significant reduction in the board space used [12]. Where once even a “simple” smart product needed a microcontroller (MCU), a power management IC (PMIC), an RFIC, and a chip to control the user interface at the least, can now be served by a single-chip solution, requiring only a display, antenna, and a battery (packaging too) to create a basic product.

All of the developments in component integration, next-generation functionalities, and even packaging advances come together to create the micro-product revolution going on as you read this. Another often-overlooked aspect in the effort to shrink a product involves flexible electronics. Making flat, flexible, and efficient electronics opens the door to countless smart products that were impractical due to size or form-factor issues.

The ability to bend, fold, roll, and even stretch will enable electronics to not only expand more deeply into market sectors like medical and sports wearables, advanced portable and small robotics applications, and the Internet of Things, it will also enable those products to be rolled up and/or folded and easily stored between uses. Optimizing a product design by highly integrating its functionality at the chip, board, and product level pays major dividends.

Bulky keyboards and large screens will eventually cease to be a size issue when flexible electronics and non-contact means of data entry are further commercialized. Reducing the impact of the user interface on product design cannot be underestimated, as every external opening is removed not only reduces the form factor demands, but also increases water resistance and product durability. Optimizing a product design by highly integrating its functionality at both the chip and board level pays dividends at each.

Looking Forward

The advanced electronics and the semiconductors behind them are the sophisticated result of decades of research and development, both in functionality and scaling. The demand for smaller and smaller technology will never diminish, as the new functionalities delivered today create new expectations for tomorrow. The semiconductor industry must continue in its efforts to innovate and keep shrinking electronic components to keep pace with the demands of society in the areas of technological advancement, in even the tiniest of ways.

[Reference]

[1] ScienCentral. (n.d.). The Vacuum Tube. ScienCentral and The American Institute of Physics, 1999. https://www.pbs.org/transistor/science/events/vacuumt.html
[2] National Geographic Society. (2014, July 18). World’s First Computer Bug. https://www.nationalgeographic.org/thisday/sep9/worlds-first-computer-bug/
[3] The semiconductor revolution. (n.d.). Encyclopedia Britannica. https://www.britannica.com/technology/electronics/The-semiconductor-revolution
[4] Kilby, J. (n.d.). Jack Kilby Biography. NobelPrize.Org. https://www.nobelprize.org/prizes/physics/2000/kilby/biographical/
[5] Lovos, M. (2018, June 7). Robert N. Noyce Biography. IEEE Computer Society. https://www.computer.org/profiles/robert-noyce
[6] The Electrochemical Society. (2021, April 13). Impact of Micro-/Nano-Electronics, Miniaturization Limit, and Technology Development for the Next 10 Years and after. Newswise. https://www.newswise.com/articles/impact-of-micro-nano-electronics-miniaturization-limit-and-technology-development-for-the-next-10-years-and-after
[7] Navitas. (2021, August 27). SHARGE Upgrade 100W Fast Charging: 60% Smaller than Legacy Silicon. https://navitassemi.com/navitas-and-sharge-upgrade-100w-fast-charging-60-smaller-than-legacy-silicon/
[8] SK hynix Unveils the Industry’s Most Multilayered 176-Layer 4D NAND Flash. (2020, December 24). SK Hynix Newsroom. https://news.skhynix.com/sk-hynix-unveils-the-industrys-highest-layer-176-layer-4d-nand-flash/
[9] Jha, J., Ganguly, S., & Saha, D. (2021, May 12). GaN-based complementary inverter logic gate using InGaN/GaN superlattice capped enhancement-mode field-effect-transistors. IOP Science. https://www.scribbr.com/apa-citation-generator/new/webpage/
[10] Markoff, J. (2015, September 26). Smaller, Faster, Cheaper, Over: The Future of Computer Chips. The New York Times. https://www.nytimes.com/2015/09/27/technology/smaller-faster-cheaper-over-the-future-of-computer-chips.html
[11] SK hynix. (2021, July 12). SK hynix Starts Mass Production of 1anm DRAM Using EUV Equipment. SK Hynix Newsroom. https://news.skhynix.com/sk-hynix-starts-mass-production-of-1anm-dram-using-euv-equipment/
[12] A Trend Towards Miniaturized Electronics A Trend Towards Miniaturized Electronics. (2021, May 10). ROHM Semiconductor. https://www.rohm.com/blog/miniaturized-electronics

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