AI and high-performance computing (HPC) are evolving at an unprecedented pace, pushing traditional memory technologies such as DRAM and NAND flash to their limits. To meet the growing demands of the AI era, the industry is exploring emerging memory technologies which go beyond traditional memory.

Among these new memory technologies, storage-class memory¹ (SCM) has emerged as a key development as it can bridge the performance gap between DRAM and NAND flash. Recognizing the potential of SCM, SK hynix has developed selector-only memory² (SOM), a groundbreaking innovation that redefines SCM and strengthens the company’s AI memory portfolio.

¹Storage-class memory: A class of emerging non-volatile memory technologies that combines the speed of DRAM with the persistent storage capabilities of NAND flash. It bridges the gap between DRAM and NAND flash in terms of performance, cost, and storage capacity.
²Selector-only memory (SOM): A cross-point memory device featuring a chalcogenide-based film which can perform both selector and memory functions.

This final episode of  Rulebreakers’ Revolutions  explores the journey behind SOM’s development, the key role of SK hynix’s rigorous R&D approach, and the implications for the future of AI and HPC.

The Mission: Going Beyond Traditional Memory With Next-Gen SCM

The AI era has sparked a data explosion. AI systems, from large language models³ (LLMs) to multimodal AI⁴, require high-performance memory to rapidly access and process this vast amount of data and perform complex computations. This next-generation performance must be balanced with affordability and energy-efficiency, placing further pressure on memory technologies.

³Large language model (LLM): Advanced AI systems trained on vast amounts of text data to understand and generate human-like text based on the context they are given.
⁴Multimodal AI: Machine learning models capable of processing and integrate different types of data, including text, audio, and video.

To meet these increasing demands, HPC systems are transitioning from traditional CPU-centric models to memory-centric architectures. By supporting data processing directly within memory, these memory-centric systems can minimize data movement to ultimately improve system performance and efficiency.

Amid this shift, the industry is exploring new memory technologies which can surpass the capabilities of traditional memory. Among them, SCM has emerged as a promising solution by bridging the performance gap between DRAM and NAND flash. As a non-volatile memory, SCM combines the speed and cost-efficiency of DRAM with the high capacity of NAND flash. Additionally, the advent of CXL^®5 technology has enabled seamless connections between memory and devices such as CPUs, GPUs, and accelerators, creating new opportunities for SCM adoption in advanced computing.

⁵Compute Express Link^®(CXL^®): A next-generation interface that connects the CPU, GPU, memory, and other components to efficiently enhance the performance of high-performance computing systems.

Recognizing the capabilities of the technology, SK hynix took on the challenge of developing a next-generation SCM product—SOM—which could revolutionize the industry.

SK hynix’s SOM goes beyond traditional memory, breaking the barriers to next-generation memory

Beyond 3DXP: Rigorous R&D and Collaboration Unlock SOM

Before developing SOM, SK hynix had made great progress with an alternative SCM technology—3D XPoint (3DXP). Developed in the mid-2010s, 3DXP was a non-volatile storage technology that used phase-change memory (PCM)⁶ to store data through changes in material resistance states. It employed a transistor-less, cross-point architecture⁷ featuring selectors⁸ and memory cells placed at the intersection of perpendicular wires. By stacking 3DXP cells in a three-dimensional architecture without transistors, the product offered high memory density.

⁶Phase-change memory (PCM): A technology which enables non-volatile electrical data storage at the nanometer scale. PCM memory switching involves heating materials so they switch between amorphous and crystalline states, which correspond to the binary digits 0 and 1, respectively.
⁷Cross-point architecture: A memory architecture where data is stored at the intersection, or “cross-point”, of two or more lines in a grid-like structure.
⁸Selector: A device in a memory array that regulates the flow of current to and from a memory cell. This enables precise access to a specific cell while blocking unwanted paths for more accurate read and write operations.

Despite the potential of 3DXP, SK hynix identified challenges regarding the product’s scalability beyond 20 nm process technology. As a result, the company switched its attention to an alternative next-generation SCM product.

The company set about developing SOM, a groundbreaking cross-point memory device that uses a single chalcogenide⁹ -based film, known as dual-functional material (DFM), to perform both selector and memory functions. Compared to 3DXP, SOM eliminates the need for the separate selector and PCM setup. Instead, selectors in SOM are deployed without standalone memory cells to improve selector functionality. Moreover, SOM utilizes an optimized cross-point array with lower cell stack aspect ratios¹⁰ for better scalability and higher memory density.

⁹Chalcogenide: A chemical compound consisting of at least one chalcogen anion, such as sulfur, and an electropositive element, such as metal.
¹⁰Aspect ratio: Height-to-width ratio of memory cells.

One of the biggest changes from 3DXP was the inclusion of DFM in place of phase-change material. As a result of this switch, SOM offers advanced specifications. Firstly, the write speed is significantly improved as DFM, unlike PCM, does not require time to perform phase changes. While PCM required a high write current for joule heating during phase transitions, the use of DFM significantly reduced the necessary write current. In addition, DFM offers increased stability when operating at high temperatures, reducing thermal disturbance¹¹. DFM’s improved heat resistance also ensures it offers enhanced cyclic endurance compared to PCM, boosting overall durability.

¹¹Thermal Disturbance: A phenomenon where heat generated while programming one memory cell unintentionally affects the state of neighboring cells due to heat diffusion, potentially disrupting their data integrity.

SOM replaces the phase-change material used in 3DXP with DFM

The successful development of SOM would not have been possible without SK hynix’s rigorous approach to R&D and smooth internal collaboration. For example, the company discovered DFM during research on chalcogenide-based selector and memory materials. By applying a new bipolar operation instead of the conventional unipolar operation, the team found it could achieve both selector and memory characteristics simultaneously.

The company’s R&D approach also enabled a significant reduction in SOM’s power consumption compared to pre-development expectations. When conventional optimization approaches proved insufficient, this prompted a radical reexamination of materials, design, and operational algorithms. In response, various research teams came together to collaborate on the project and develop new approaches. They tested the application of new materials and operational techniques through simulations, addressing any potential issues. This meticulous process cut power consumption by approximately one-third from initial predictions, a crucial advancement in the development of SOM.

Unveiling the World’s Smallest SOM

SK hynix has successfully developed the world’s smallest SOM, the first fully integrated¹² 16nm half-pitch¹³ SOM. This revolutionary achievement in the SCM field was presented at the prestigious 2024 IEEE Symposium on VLSI Technology and Circuits (2024 VLSI Symposium).

¹²Fully integrated: Complete integration of circuits and manufacturing processes at the cell array level, unlike basic single-cell prototypes in academic research.
¹³Half-pitch: Half of the minimum center-to-center distance between interconnect lines in a semiconductor.

Compared to 3DXP, SOM offers a reduction in write speed from 500 nanoseconds (ns) to 30 ns and write current, which dropped from 100 microamps (µA) to 20 µA. In addition, cyclic endurance increased from 10 million to over 100 million cycles, highlighting SOM’s increased durability. SOM was also shown to have advanced persistency, the ability to retain data under extreme conditions, as tests proved it could retain data for over 10 years at 125°C.

SOM offers outstanding capabilities from rapid write speed to advanced persistency

Significantly, the 16nm SOM is the smallest, most scalable and high-performing cross-point memory solution on the market. As the AI landscape continues its evolution, the successful development of SOM strengthens SK hynix’s AI memory leadership, complementing products such as HBM, AiMX, and CXL Memory Module (CMM)-DDR5.

Looking forward, the research behind SOM will contribute to broader advancements in next-generation memory technology. Its impact extends to the growing field of heterogeneous integration, enabling innovative system integration approaches that cater to AI data centers and diverse AI solution providers. As computing architectures shift towards memory-centric computing, SOM’s technological breakthroughs will play a crucial role in shaping the future of AI and HPC.

Rulebreaker Interview: Myoungsub Kim, Global Revolutionary Technology Center (RTC)

To find out more about the company’s innovative approach to SOM development, the SK hynix Newsroom spoke with Myoungsub Kim of the Global Revolutionary Technology Center (RTC), which conducts R&D of next-generation semiconductors. Kim discusses the major challenges faced when developing SOM as well as the rulebreaking mindset adopted by employees.

<Other articles from this series>

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[Rulebreakers’ Revolutions] How SK hynix Broke Barriers in Mobile DRAM Scaling With World-First HKMG Application

[Rulebreakers’ Revolutions] Innovative Design Scheme Helps HBM3E Reach New Heights

[Rulebreakers’ Revolutions] How SK hynix’s Server DRAM Validation Process Succeeds in a Diverse Server CPU Market

[Rulebreakers’ Revolutions] Flexible & Collaborative eSSD Virtualization Development for Today’s Data Centers

[Rulebreakers’ Revolutions] How SK hynix’s Design Innovations Pushed GDDR7 to New Limits of Speed

[Rulebreakers’ Revolutions] How CXL Tech Expands Data Center Memory Scaling Boundaries in the AI Era

The post [Rulebreakers’ Revolutions] How SK hynix’s SOM Paves the Way for Next-Gen Memory in the AI Era first appeared on SK hynix Newsroom.

¹Memory hierarchy: Memory can be divided into a hierarchy based on speed as well as use. A typical memory structure includes cloud, flash, DRAM, cache and register memories.
²Compute Express Link (CXL): PCIe-based next-generation interconnect protocol on which high-performance computing systems are based.
³3D XPoint (3DXP): Developed by Intel and Micron, 3DXP is a non-volatile phase change technology that serves as both memory and storage. Cell arrays consist of simple stackable crossbar structures for multiple layers.

This article will focus on research into developing a four-deck 3DXP solution which was presented at the 2023 Very Large-Scale Integration (VLSI) Symposium, one of the world’s top three semiconductor conferences. It also considers the scaling limitations of 3DXP and the potential for selector-only memory (SOM) to be the future of storage class memory (SCM).

Advancing 3DXP Through Novel Integration Schemes

Figure 1. (Left) Cross section transmission electron microscopy (TEM) of two-deck and four-deck cell arrays with a copper multi-layer and peri under cell (right) Floorplan of a 20 nm four-deck chip with a capacity of 256 Gb

SK hynix has made significant progress in its development of 3DXP memory solutions over the past few years. At the 2018 International Electron Devices Meeting (IEDM), SK hynix shared the results of its two-deck 64 Mb test chip operation with 2z⁴ nanometer (nm) technology, and then successfully demonstrated a 128 Gb chip in 2019. More recently, the company demonstrated progress on a four-deck 256 Gb chip with 20 nm technology at the 2023 VLSI.

⁴2z: The third generation of 20 nm process technology in which “z” refers to the lower third number range of the 20 nm class, which covers 20 nm-29 nm. The letters “x”, “y” and “z” are used to refer to the upper, middle, and lower thirds, respectively, of the relevant process technology class such as 10 nm, 20 nm etc.

Figure 2. (Left) Voltage distribution of each deck after set and reset operations (right) Basic die information, including structure and operation properties, of the four-deck chip

To create this latest solution, SK hynix developed novel integration schemes including new self-align etching, cleaning, chemical mechanical polishing (CMP), and interlayer dielectric (ILD) deposition. A low-resistance conductor material was also developed for the interconnection scheme to ensure a sufficient flow of write current while minimizing spike current. In addition, a large read window margin⁵ and a tight voltage distribution of the 1 Gb array for each deck were achieved by carefully controlling the 20 nm pillar patterning process, material design, and appropriate write/read operation.

⁴Read window margin (RWM): The threshold voltage (Vt) interval (ΔVt) at distribution tails. When using a chalcogenide material such as PCM, it has a Vt distribution similar to DRAM or NAND. The Vt interval between the Vt distribution of 0 and 1 is regarded as the sensing margin, or the read window margin.

Overcoming Limitations of 3DXP With SOM

Figure 3. Scaling challenges of 3DXP presented in three graphs: (left) Aspect ratio (center) Set program margin (right) Thermal disturbance

Although the researchers successfully demonstrated a four-deck 256 Gb device, they discovered issues when assessing the scalability of 3DXP beyond 20 nm technology. First, the structure of 3DXP, which consists of phase-change memory (PCM)⁶ and an ovonic threshold switch (OTS)⁷, will have a much higher aspect ratio⁸ as the technology is scaled down and this will lead to complex progress integration. Second, 3DXP will have a smaller write program margin between set and reset operations as the technology node shrinks. Third, the scaling limit by thermal disturbance is expected to occur at technology nodes beyond 1y nm without the elusive thermal conductivity of inter-layer dielectric.

⁶Phase-change memory (PCM): A technology which enables nonvolatile electrical data storage at the nanometer scale. A PCM device consists of a small active volume of phase-change material placed between two electrodes. A common PCM material is germanium-antimony-tellurium (GeSbTe).
⁷Ovonic threshold switch (OTS): A two-terminal symmetrical voltage sensitive switching device which, after being brought from the highly resistive state to the conducting state, returns to the highly resistive state when the current falls below a holding current value.
⁸Aspect ratio (AR): The ratio of height to width. A high aspect ratio means that the structure is narrow but tall.

Figure 4. Memory requirement relationship between performance, which indicates bandwidth, and cost

As a result of these limitations, SK hynix is preparing SOM as an alternative solution for the next generation of storage class memory. SOM is composed of only two electrodes and a single dual-functional material which can operate as both the memory and selector. Compared to 3DXP, SOM offers lower write latency and cell power consumption as it eliminates 3DXP’s long crystallization time for the set operation and high reset current. Therefore, SOM is set to be a leading solution for next-generation applications with scaling longevity beyond 1z nm technology.

For more information regarding RTC’s research, please visit the center’s research website (https://research.skhynix.com). The RTC operates the site to share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.

The post Beyond 20nm 3DXP: Why Selector-Only Memory is the Future for Ultra-Fine Processes first appeared on SK hynix Newsroom.