• The company plans to supply the highest-performing, highest-capacity 12-layer HBM3E to customers by the end of the year
• DRAM chips made 40% thinner to increase capacity by 50% at the same thickness as the previous 8-layer product
• The company to continue HBM’s success with outstanding product performance and competitiveness

Seoul, September 26, 2024

SK hynix Inc. (or “the company”, www.skhynix.com) announced today that it has begun mass production of the world’s first 12-layer HBM3E product with 36GB¹, the largest capacity of existing HBM² to date.

¹Previously, the maximum capacity of HBM3E was 24GB from eight vertically stacked 3GB DRAM chips.
²HBM (High Bandwidth Memory): This high-value, high-performance memory vertically interconnects multiple DRAM chips and dramatically increases data processing speed in comparison to traditional DRAM products. HBM3E is the extended version of HBM3, the fourth generation product that succeeds the previous generations of HBM, HBM2 and HBM2E.

The company plans to supply mass-produced products to customers within the year, proving its overwhelming technology once again six months after delivering the HBM3E 8-layer product to customers for the first time in the industry in March this year.

SK hynix is the only company in the world that has developed and supplied the entire HBM lineup from the first generation (HBM1) to the fifth generation (HBM3E), since releasing the world’s first HBM in 2013. The company plans to continue its leadership in the AI memory market, addressing the growing needs of AI companies by being the first in the industry to mass-produce the 12-layer HBM3E.

According to the company, the 12-layer HBM3E product meets the world’s highest standards in all areas that are essential for AI memory including speed, capacity and stability. SK hynix has increased the speed of memory operations to 9.6 Gbps, the highest memory speed available today. If ‘Llama 3 70B’³, a Large Language Model (LLM), is driven by a single GPU equipped with four HBM3E products, it can read 70 billion total parameters 35 times within a second.

³Llama 3: Open-source LLM released by Meta in April 2024, with 3 sizes in total: 8B (Billion), 70B, and 400B.

SK hynix has increased the capacity by 50% by stacking 12 layers of 3GB DRAM chips at the same thickness as the previous eight-layer product. To achieve this, the company made each DRAM chip 40% thinner than before and stacked vertically using TSV⁴ technology.

The company also solved structural issues that arise from stacking thinner chips higher by applying its core technology, the Advanced MR-MUF⁵ process. This allows to provide 10% higher heat dissipation performance compared to the previous generation, and secure the stability and reliability of the product through enhanced warpage controlling.

⁴TSV (Through Silicon Via): This advanced packaging technology links upper and lower chips with an electrode that vertically passes through thousands of fine holes on DRAM chips.
⁵MR-MUF (Mass Reflow Molded Underfill): The process of stacking semiconductor chips, injecting liquid protective materials between them to protect the circuit between chips, and hardening them. The process has proved to be more efficient and effective for heat dissipation, compared with the method of laying film-type materials for each chip stack. SK hynix’s advanced MR-MUF technology is critical to securing a stable HBM mass production as it provides good warpage control and reduces the pressure on the chips being stacked.

“SK hynix has once again broken through technological limits demonstrating our industry leadership in AI memory,” said Justin Kim, President (Head of AI Infra) at SK hynix. “We will continue our position as the No.1 global AI memory provider as we steadily prepare next-generation memory products to overcome the challenges of the AI era.”

About SK hynix Inc.

SK hynix Inc., headquartered in Korea, is the world’s top-tier semiconductor supplier offering Dynamic Random Access Memory chips (“DRAM”), flash memory chips (“NAND flash”), and CMOS Image Sensors (“CIS”) for a wide range of distinguished customers globally. The company’s shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxembourg Stock Exchange. Further information about SK hynix is available at www.skhynix.com, news.skhynix.com.

Media Contact

SK hynix Inc.
Global Public Relations

Technical Leader
Sooyeon Lee
E-Mail: global_newsroom@skhynix.com

Technical Leader
Kanga Kong
E-Mail: global_newsroom@skhynix.com

The post SK hynix Begins Volume Production of the World’s First 12-Layer HBM3E first appeared on SK hynix Newsroom.

¹HBM: A high-value, high-performance product that revolutionizes data processing speeds by connecting multiple DRAM chips with through-silicon via (TSV).

Since developing the world’s first HBM in 2013, SK hynix has led the way in developing the next generations of the technology. In March 2024, the company became the first to mass-produce and supply HBM3E, the fifth generation of HBM which offers the industry’s highest levels of performance.

SK hynix’s leadership in this area is due to its extensive history of preparing key packaging technologies such as TSV and MR-MUF². To find out more, the SK hynix Newsroom caught up with Gyujei Lee, head of Package Product Development, to discuss the company’s technological innovations in packaging for AI memory.

²Mass Reflow-Molded Underfill (MR-MUF): A process involving injecting a liquid protective material between stacked chips, which is then hardened. Compared to the traditional method of placing film-like materials between each layer, MR-MUF is a more efficient process and more effective at heat dissipation.

Lee cites the importance of SK hynix’s innovative packaging technologies for HBM’s success

Foundation for HBM Leadership: Bold Investment in Packaging Technology and R&D

SK hynix’s core HBM packaging technologies

SK hynix applied TSV technology to the first generation of HBM, which was developed by the company as a world-first in 2013. A key technology that enables the rapid speed of HBM products, TSV involves drilling thousands of microscopic holes in a DRAM chip to connect the electrodes that vertically penetrate the holes of the chip’s upper and lower layers.

Although TSV has been touted as a next-generation technology to overcome the performance limitations of conventional memory for more than 20 years, it did not immediately emerge as a commercialized technology. The challenges of building the technical infrastructure and the uncertainty of recouping the investment prevented companies from taking the plunge. Lee described the situation as “like a bunch of kids around a big lake, waiting to see who would jump in first.”

“SK hynix was also one of the companies to hesitate in the beginning,” he recalled. “However, to prepare for the future market, we decided to secure both TSV technology, which can simultaneously enable top performance and high capacity, and WLP³ technology, which includes stacking. Therefore, we took the initiative and began active research from the early 2000s.”

³Wafer-level package (WLP): Technology that produces end products by packaging and testing a wafer all at once before the wafer is diced. It differs from the conventional packaging method of processing a wafer and dicing each chip.

As the market for high-performance graphics processing unit (GPU) computing grew in the 2010s, there was a rising need for high-bandwidth near-memory⁴ to support it. To meet this demand, SK hynix began developing a new product combining TSV and WLP technologies, ultimately leading to the creation of the first HBM. This new product was more than four times faster than GDDR5, the fastest graphics DRAM product at the time, while consuming 40% less power. Moreover, the first HBM dramatically reduced the product area through chip stacking.

⁴Near-memory: Memory that is close to the computing device (processor), allowing for faster data processing.

From MR-MUF to Advanced MR-MUF: Driving HBM Success

Although SK hynix was the first to usher in the HBM era, the company did not take the lead in the growing market until it developed the third generation of HBM, HBM2E, in 2019. This marked a turning point for the company as it was considered to have gained a clear industry advantage. However, Lee recalls the various bumps in the road to this achievement.

Lee revealed how MR-MUF was a crucial breakthrough for the company’s HBM lineup

“We succeeded in developing the first HBM, but then we needed to raise the quality and mass production capability to a level that would satisfy the market and our customers,” he said. “This led us to develop a new packaging technology that was expected to be better than the existing one in terms of stability in material application and ease of technical implementation. But unexpectedly, we encountered reliability difficulties in the early stages and had to find a new breakthrough.

“At that time, the company was also developing MR-MUF technology according to its technology roadmap. To respond promptly to customers, leaders from the relevant departments quickly analyzed technology-related data and simulation results to verify the reliability of MR-MUF, and convinced management and customers. So, the technology was able to be applied to HBM2E in a timely manner.”

Lee cites the development of MR-MUF as a key turning point for SK hynix’s HBM success story

“Thanks to the management and customers who believed in our development team, we were able to successfully bring our unique MR-MUF technology to the market,” said Lee. “This has enabled the mass production and supply of HBM2E, which offers stable levels of quality and performance.”

Due to the application of MR-MUF, HBM2E became a game-changer in the HBM market. It is therefore clear that MR-MUF played a key role in making SK hynix’s “HBM success story” possible.

Lee explains the MR-MUF technology roadmap

In 2023, SK hynix maintained its unrivaled leadership in HBM by first developing the 12-layer HBM3, followed by the development of HBM3E, the fifth generation of HBM. Lee and the development team believe these successes were largely due to the development of Advanced MR-MUF⁵, an improved version of the existing MR-MUF technology.

⁵Advanced Mass Reflow-Molded Underfill (MR-MUF): Next-generation MR-MUF technology with warpage control that can stack chips 40% thinner than previous generations of HBM products without warpage, as well as new protective materials for improved heat dissipation.

“The 12-layer HBM3 required enhanced heat dissipation performance due to the increased number of stacked chips,” he said. “In particular, it was not easy to handle the warpage issue of the thinner chips in the 12-layer HBM3 with the existing MR-MUF method.

“To overcome these limitations, we developed an Advanced MR-MUF technology that improves on the existing MR-MUF. This also led to the successful development and mass production of the world’s first 12-layer HBM3 in 2023, followed by the mass production of the world’s highest-performing HBM3E in March 2024. Moreover, Advanced MR-MUF is applied to the 12-layer HBM3E, which will be supplied to major AI companies from the second half of this year. Going forward, Advanced MR-MUF will be applied to a wider range of applications, further solidifying SK hynix’s leadership in HBM technology.

“Recently, there was a rumor in the industry that MR-MUF is difficult to implement. To overcome this, we focused on communicating to customers that MR-MUF is the optimal technology for high stacking, and eventually reaffirmed customers’ trust.”

Next-Gen Tech & Customer Partnerships Key to Custom Product Development

Lee won SK Group’s 2024 SUPEX Award for his contribution to developing HBM

For his longstanding contributions to HBM development, Lee was awarded SK Group’s highest honor, the 2024 SUPEX Award⁶, in June 2024 along with SK hynix’s core HBM technical members. Commenting on receiving the award, Lee said: “It is thanks to the efforts of many members who have worked as one team to make the product a success.”

⁶SUPEX Award: As the most prestigious award within SK Group that carries the meaning “super excellent,” it recognizes members who have successfully realized innovations by not being afraid to take on new challenges.

However, Lee said there is no room for satisfaction or complacency. For SK hynix to maintain its HBM leadership in the future, he emphasized the importance of timely development of various next-generation packaging technologies to meet the ever-increasing demand for customized products.

“Next-generation packaging technologies such as hybrid bonding⁷ have recently gained attention as a way to stack chips higher for increased performance and capacity while maintaining product thickness according to standard specifications,” he stated. “Although heat control is still a challenge due to the narrower gap between the chips, these new packaging technologies are expected to solve the issue and meet the increasingly diverse performance needs of customers.

⁷Hybrid Bonding: A technology that connects chips together directly without bumps between them. This reduces the overall thickness of the chip, enabling high-layer stacking, and is therefore being considered for HBM products with 16 layers or more. SK hynix is currently reviewing both Advanced MR-MUF and hybrid bonding technologies.

“SK hynix will continue to enhance its existing Advanced MR-MUF with excellent heat dissipation performance, while also securing new technologies.”

Lee claimed that strong customer communication will continue to be crucial for the company’s growth

Lastly, Lee emphasized that close communication and collaboration with customers is one of SK hynix’s strengths and a competitive advantage that the company should continue to strengthen in the future.

“I think the biggest driving force behind SK hynix’s dominance in the HBM market is its ability to promptly deliver high-quality products with mass production competitiveness to customers when there was actual demand,” he said. “This has been possible not only because of our technological capabilities, but also due to our continuous communication with customers.

“Our packaging development department is also quick to identify customer and stakeholder needs and incorporate them into product features. When this effort is combined with our unique culture of collaboration, I think we’ll be a powerful force in any situation. I will continue to share my motto, ‘feel together, move vigilantly’ with our employees as we prepare for the future of SK hynix packaging.”

The post SK hynix VP Gyujei Lee Targets Continued HBM Success With Next-Gen Packaging Technology first appeared on SK hynix Newsroom.

The SK hynix Newsroom is running a series of interviews with the Top Team—the executives in charge of the company’s major business divisions. This series provides insights into the business strategies, organizational culture, and more promoted by the leaders to achieve the company’s vision. For this latest interview, the newsroom spoke with Vice President and Head of Package & Test (P&T) Woojin Choi.

For the past 30 years, Woojin Choi has conducted and led R&D in semiconductor memory packaging. During that time, packaging has become increasingly important and is now a pivotal technology for in-demand AI memory solutions such as HBM¹.

¹High Bandwidth Memory (HBM): A high-value, high-performance product that revolutionizes data processing speeds by connecting multiple DRAM chips with through-silicon via (TSV).

As the technology environment has evolved, packaging has become a game-changer in the AI memory market. Amidst this backdrop, Choi, who was appointed as head of SK hynix’s Package & Test (P&T) at the end of 2023, is determined to prove the company’s technological edge. In this latest Top Team Insights interview, the newsroom spoke with Choi about the importance of packaging technologies in the AI era, taking on new challenges, and his mission to go “beyond HBM”.

Leading the AI Memory Market through Limitless Challenges

After wafers undergo the semiconductor front-end process in fabs, P&T oversees the back-end process where wafers are packaged into products and tested to ensure they meet customer expectations.

While packaging traditionally held the role of electrically connecting chips and protecting them from external shocks, it is now vital to enabling differentiated product performances. Consequently, advanced packaging technologies such as TSV² and MR-MUF³ have grown in importance as they have proven to be critical in the development of key products including HBM.

²Through-silicon via (TSV): A technology that drills microscopic holes in DRAM chips to vertically connect silicon dies through electrodes.
³Mass Reflow-Molded Underfill (MR-MUF): Mass reflow is a technology that connects chips together by melting the bumps between stacked chips. Molded underfill fills the gaps between stacked chips with protective material to increase durability and heat dissipation.

Choi believes that facing new challenges will enable a company to become an industry leader in the AI era

“P&T technology is turning into a crucial factor in the battle for semiconductor leadership,” Choi claimed. “As demand for high-performance chips is exploding in the AI era, we will contribute to the development of the highest-performance memory products through advanced packaging technologies.

Choi emphasizes to his employees the importance of setting no limits to challenges. “The way we have aggressively taken on tough challenges has lifted the Korean semiconductor industry to where it is today,” he said. “At a time when countries around the world are investing huge amounts of capital to secure leadership in the semiconductor market, it has become even more vital to continuously embrace new challenges.”

According to Choi, the global semiconductor race has even been likened to a war due to its intense environment. “If continuous innovations and efforts to overcome challenges cease, it could be disastrous for a company,” he said. “It is more crucial than ever to push the limits in all areas of product development including performance, yield, and cost competitiveness.”

Choi says that advanced packaging technologies are key to developing next-generation signature memories

As AI memory is a key pillar in the global semiconductor race, Choi presented the development of signature memories as a key strategy to revolutionize this technology.

“In the age of AI, SK hynix is focusing on signature memories which possess diverse aspects required by customers, including various capabilities, sizes, shapes and power efficiency,” Choi explained. “To realize these products, we are advancing technologies such as TSV and MR-MUF which play a key role in HBM performance. Moreover, we are developing various next-generation packaging technologies including chiplet⁴ and hybrid bonding⁵. These innovations will contribute to the development of new types of semiconductors while supporting heterogeneous integrations such as between semiconductor memory and logic chips.”

⁴Chiplet: A technology that breaks up chips into functions and connects these separated pieces called chiplets on a single substrate to enable heterogeneous bonding and integration.
⁵Hybrid Bonding: A technology that connects chips together directly without bumps to enable higher bandwidth and capacity. This allows for shorter data pathways and the ability to stack more chips in the same space.

Choi stresses that his department will not limit themselves when taking on challenges and will demonstrate their strong technological advantage.

The Next Innovation and Challenge: Building a Global Manufacturing Base

Choi’s emphasis on challenges makes sense when looking at his career. In 2020, he succeeded in developing a heat dissipation solution for HBM3 to improve the product’s performance. He also helped tackle the industry downturn in 2023 by reducing costs in areas including materials and general expenses. Additionally, he quickly secured a production line to meet the growing demand for DRAMs during the rapid rise of ChatGPT, helping SK hynix strengthen its leadership in AI memory.

“It was challenging to respond immediately to the sudden surging demand for AI memory in 2023, but we quickly utilized our TSV packaging line with no additional investments to ramp up the production of our server-oriented 3D stacked memory (3DS)⁶ modules based on DDR5 DRAM,” Choi recalled. “This is an example of a bold decision made in a short period of time. We would not have been able to accomplish this feat if we had hesitated.”

⁶3D Stacked Memory (3DS): A high-bandwidth memory product that is packaged by connecting two or more DRAM chips through TSV. 3DS and HBM differ in that the latter is supplied to the system company before packaging is completed, and it is then packaged with logic chips such as GPUs.

Choi has an instrumental role in the planning of SK hynix’s new manufacturing facility in Indiana

Now, Choi’s challenge awaits overseas. On April 3, SK hynix announced plans to establish a packaging manufacturing facility in the U.S. state of Indiana to enhance its competitiveness in the global HBM market while also enhancing its R&D capabilities in advanced packaging.

Choi is playing a key role in this process by planning the strategy for the construction and operations of the fab. The U.S. packaging plant will receive HBM wafers that have undergone the front-end process from the Korean HQ to produce finished products and, at the same time, actively cooperate in R&D with global companies.

“We are currently in the process of refining the fab design and mass production system, as well as preparing to build an R&D cooperation ecosystem with global companies,” Choi explained. “Once the factory is fully operational, we expect it to make a significant contribution to strengthening the company’s AI memory technology and business leadership.”

Going “Beyond HBM”: Data-Centric Innovations and Focus on Employee Development

As for the important missions of P&T, Choi mentioned maximizing profitability and what he calls going “beyond HBM.” “In the short term, we plan to strengthen our domestic production capabilities to meet demand for HBM while leveraging our global base to maximize profitability,” he said. “In the long run, we aim to secure more innovative packaging technologies like MR-MUF, which is now a vital technology to HBM.”

To accomplish this, Choi highlights the significance of finding answers in the data, a philosophy he has followed throughout his decades of experience in the packaging field.

“As there is a tremendous amount of data during the P&T process, the saying that the ‘answer is in the data’ proves to be true,” Choi said. “If we utilize this data well, we can improve yields and even find clues for new product development. We need to work with the idea that data can guide us to growth.”

To go “beyond HBM,” Choi emphasizes utilizing data for growth and focusing on membership development

Lastly, Choi underlined his commitment to supporting the growth of SK hynix employees. “It is our members who have raised the profile of packaging technology,” he said. “Many of the breakthroughs we have made, such as solving the heat dissipation issue of HBM at the packaging stage, have come from their ideas.” Accordingly, Choi plans to lay the foundation for continued growth so employees can always take on challenges with the mindset of leading the global market.

“Our company is actively interacting with universities and research institutes at home and abroad,” he added. “We plan to capitalize on this to help P&T members gain diverse global experiences and further improve their R&D capabilities to aid their growth and development.”

The post Top Team Insights: “Embrace Limitless Challenges to Strengthen Advanced Packaging Tech,” Motto of P&T Head Woojin Choi first appeared on SK hynix Newsroom.

SK hynix has ramped up preparations for its evolution in the AI era with a new addition to its executive team. Hoyoung Son became the head of Advanced Package Development at the start of 2024 to strengthen the company’s leadership in packaging technology for HBM¹, a key semiconductor for AI.

¹High Bandwidth Memory (HBM): A high-value, high-performance product that revolutionizes data processing speeds over conventional DRAMs by vertically connecting multiple DRAMs with through-silicon via (TSV) technology. There are five generations of HBM, starting with the original HBM and followed by HBM2, HBM2E, HBM3, and HBM3E—an extended version of HBM3.

In 2023, Son received the distinguished Haedong Young Engineer Award² for his contributions to the development of advanced packaging³ technology, which is also a key element for HBM products. In the fourth article of this interview series with recently appointed executives, Son spoke about his plans for the future and how he will adapt to such a big role in the AI era.

²Haedong Young Engineer Award: A prize presented at the annual Haedong Awards. Hosted by the Haedong Science and Culture Foundation, the awards recognize those who have made significant contributions to promote the growth and expansion of electronic engineering in South Korea.
³Advanced packaging: A solution that emerged to meet market requirements for high-performance products by resolving issues related to limits on wafer density technology.

“It was a special moment to become the first team leader to win the Haedong Young Engineer Award in 2023, which is usually awarded to executives,” he said. “This year, I have a greater sense of responsibility now that I am an executive. I will do my utmost to accomplish my goals in this new position.”

An Unwavering Spirit Sparking a Revolution in AI Semiconductor Memory

Son has been instrumental in the development of HBM, which has garnered significant attention in the semiconductor industry. He helped solidify the company’s leadership in AI memory technology by leading the development of TSV⁴, the core technology of HBM, as well as SK hynix’s proprietary MR-MUF⁵ from the early stages of their introduction.

⁴Through Silicon Via (TSV): A technology that drills thousands of microscopic holes in a DRAM chip and vertically connects silicon dies through electrodes.
⁵Mass Reflow-Molded Underfill (MR-MUF): The process of placing a liquid protective material between stacked chips while simultaneously hardening the chips and the surrounding circuitry. MR-MUF is considered to be more efficient than laying down a film-like material after each chip is stacked, and has exceptional heat dissipation capabilities.

Son claims his team’s perseverance will realize more breakthroughs in AI memory

“Personally, I believe the most meaningful achievement was developing the first generation of HBM in 2013, which felt like going from zero to one,” he recalled. “Countless trials and risks couldn’t stop our efforts as we used these setbacks as lessons to come up with stronger solutions. Subsequently, we successfully developed the current fifth generation of HBM, HBM3E, and advanced packaging technology.”

Son thinks that the same unwavering spirit is needed in the AI era. As unforeseen challenges await in the future, it will be important to overcome them to achieve innovations.

“Just as SK hynix never gave up on developing HBM because we believed in its value, I will continue to develop the next generation of AI memory that will lead the rapidly changing AI era,” he added.

Evolving Into a Total AI Memory Provider

Son also thinks that SK hynix’s role in the AI age is gradually changing. He believes that the company should evolve from its current position as a supplier of semiconductors to become a total AI memory provider.

Son stresses the need to develop diverse AI memory products for AI technology

“When we developed our advanced packaging technology in 2023, one division was responsible for integrating it with existing process technology. Although this approach can reduce trial and error in the early stages of development, it has flaws in terms of efficiency and expertise as the technology becomes more sophisticated and diverse,” he said. “Developing customer-specific AI memory requires a new approach as the flexibility and scalability of the technology becomes critical.”

Son stressed that as AI technology is being utilized in more areas, the hardware required to implement these technologies is also advancing in various ways. “To proactively respond to these changes, we plan to departmentalize our current divisions and enhance their expertise,” he explained.

“For different types of AI to be realized, the characteristics of AI memory also need to be more diverse,” he stated. “Our goal is to have a range of advanced packaging technologies to respond to the shifting technological landscape. Looking ahead, we plan to provide differentiated solutions to meet all customer needs.”

Building Solid Foundations for the Next Generation to Grow

As for his aspirations as a new executive, Son wants to create an environment for growth and development. More specifically, he wants the next generation of workers to have the opportunity to be creative, and emphasized the importance of working autonomously and extending their reach by having various exchanges with academic and industry experts.

“On top of securing immediate results, possessing a technological edge will be more important in the long run,” he explained. “When I was first developing TSV technology and HBM, working in an open environment that allowed me to communicate with academics and other experts was a huge asset to me.”

Son hopes to create the same work culture in his new division. “Although our current members are already highly qualified, I want to help them experience interactions with various external experts so they can become world-class engineers,” he said. “Most importantly, I want to create an environment and culture where people can work as they wish and grow together.”

Son underlines the importance of creating a work environment that encourages growth and happiness

Concluding the interview, Son emphasized that employee happiness is paramount.

“I think happiness starts with understanding the value of life and contemplating ways to grow,” he said. “We have accomplished a lot so far, but if we stay on course to continue achieving more and strive to be better by self-examining ourselves, I think we can be very content. It is my hope that our members will be happier this year.”

<Other articles from this series>

New Leadership Spotlight: SK hynix’s First Female Research Fellow, Vice President Oh Haesoon, on Advancing NAND Flash

New Leadership Spotlight: SK hynix’s Youngest Exec, Lee Donghun, Discusses Spearheading NAND Flash Development

New Leadership Spotlight: Vice President Kitae Kim, Head of HBM Sales & Marketing, on Future-Proofing HBM’s Market Leadership

Leadership Spotlight: Deoksin Kil, Head of Material Development, On Achieving Tech Innovation Through Advanced Materials

New Leadership Spotlight: Head of HBM PI Unoh Kwon Aims to Finish SK hynix’s HBM Roadmap & Lead in the AI Era

New Leadership Spotlight: Global RTC Head Jaeyun Yi Aims to Present a New Paradigm for the Future of Semiconductors

New Leadership Spotlight: SK hynix Execs Join Roundtable to Discuss Company’s AI Memory Leadership & Future Market Trends

The post New Leadership Spotlight: Vice President Hoyoung Son Targets SK hynix’s Evolution Into Total AI Memory Provider Through Advanced Packaging Tech first appeared on SK hynix Newsroom.

Fan-in Wafer-Level Chip-Scale Package (WLCSP) Process

In a fan-in WLCSP, a tested wafer enters the packaging line and a layer of metal film is created using sputtering. A thick layer of photoresist is then applied to the metal film as the photoresist must be thicker than the metal wiring used for packages. Photolithography is used to form patterns on the photoresist, and these exposed areas are copper electroplated to form the metal wiring. Next, the photoresist is stripped, and the excess thin metal film is removed using chemical etching. A dielectric layer is then formed on top, and photolithography is used to remove only the areas where the solder balls will be placed. Thus, this layer is also referred to as “solder resist.” It serves as the WLCSP’s passivation layer, or final protective layer, and distinguishes the area where the solder ball will be placed. Without this layer, solder balls would continue to melt on top of the metal layer and would not retain their globular shape when they are attached using methods such as reflow soldering.

Solder balls are attached to the dielectric layer through solder ball mounting after the layer forms a pattern through photolithography. Once the solder balls are mounted, the packaging process is complete and individual fan-in WLCSPs can then be created by dicing the wafer.

Solder Ball Mounting Process

▲ Figure 1. A bird’s eye view of wafer-level reflow equipment (Source: Hanol Publishing)

The process of solder ball mounting involves attaching solder balls onto a WLCSP for packaging. The key distinction from placing solder balls on a substrate in conventional packaging lies in the fact that solder balls are placed atop a wafer. Thus, flux application, solder ball mounting, and the reflow process follow the same steps, except that the stencil utilized to applying flux and mounting solder balls has the same size as the wafer itself.

Additionally, the reflow equipment takes a hot plate-based approach, as depicted in Figure 1, as opposed to the convection reflow method involving conveyers. In wafer-level reflow equipment, different temperatures are applied to wafers as they progress through the various stages. This ensures that packaging can progress while maintaining a temperature profile for the reflow process.

Flip Chip Bump Process

The process of forming bumps in a flip chip package is carried out in the wafer-level process, while the subsequent steps are conducted in the conventional packaging processes.

▲ Figure 2. An overview of the flip chip packaging process

▲ Figure 3. The steps for forming a flip chip bump

As the bumps must be sufficiently high, it is necessary to select a photoresist that can be thickly applied to the wafer-level package. Copper pillar bumps (CPB)¹ are formed through copper plating followed by solder plating. This solder is typically a lead-free tin/silver alloy. Once plating is complete, the photoresist is removed and the under bump metallurgy (UBM)² film formed by sputtering is removed via metal etching. The bumps are then molded into a spherical shape using wafer-level reflow equipment. The solder bump reflow process here serves to minimize height discrepancies among the bumps, reduce the surface roughness of the solder bumps, and eliminate oxides from the solder, all of which enhance the bonds during the flip chip bonding process.

¹Copper pillar bump (CPB): The structure of the bump for flip chip bonding to reduce the gap between the bumps. Copper is used to form the pillars that have bumps on top of them.
²Under bump metallurgy (UBM): The metal layer formed under flip chip bumps.

Redistribution Layer (RDL) Process

▲ Figure 4. An overview of the packaging process using a redistribution layer (RDL)

▲ Figure 5. The steps for forming a redistribution layer (RDL)

Used for chip stacking, the redistribution layer (RDL) process creates a new pad by forming an extra layer of metal wiring over a pad formed on a wafer. Consequently, the packaging processes after the RDL process follow conventional packaging processes, as depicted in Figure 4. During chip stacking, the die attach and wire bonding steps are repeated equally for each chip that needs to be stacked.

In the RDL process, sputtering is first used to create a thin layer of metal film, which is covered with a thick layer of photoresist. A pattern is created through photolithography so that the exposed areas of the pattern can be electroplated with gold to form metal wiring. Since redistribution itself is a process of rebuilding the pad, the ability to form strong bonds is essential for wire bonding. This is why gold, which is widely applied for wire bonding, is used for plating.

Fan-out Wafer-Level Chip-Scale Package (WLCSP) Process

The process of fabricating a fan-out WLCSP begins by applying tape to a wafer-shaped carrier. After wafer dicing, the high-quality chips are attached on top of the tape at regular intervals. The spaces between the chips are filled with wafer molding, resulting in a new shape. Once the wafer molding is complete, the carrier and tape are removed. Next, metal wiring is created on the newly formed wafer using wafer equipment, followed by the attachment of solder balls for packaging. Finally, the wafers are diced into individual packages.

Wafer Molding

To create a fan-out WLCSP, wafer molding is an essential step. The wafer molding process entails placing a wafer—in the case of a fan-out WLCSP, a wafer-shaped carrier with chips attached to it—into a molding frame. An epoxy molding compound (EMC)³, which can be in the form of a liquid, powder, or granules, is then added to the frame and compression and heat are applied to mold the setup. Wafer molding is not only an essential process for fan-out WLCSPs, but it is also a requirement for a known good stacked die (KGSD)⁴ that uses TSV, which will be discussed later.

³Epoxy molding compound (EMC): A heat dissipation material based on an epoxy resin, or a type of thermosetting polymer. It seals semiconductor chips to protect them from external environmental factors such as heat, moisture, and shock.
⁴Known good stacked die (KGSD): A product comprised of stacked chips that have been tested and confirmed to be of good quality. A prime example is HBM.

Through-Silicon Via (TSV) Package Process

Figure 6 illustrates the process steps of fabricating a TSV package using a via-middle⁵ approach. First, vias are formed during wafer fabrication. Subsequently, solder bumps are formed on the wafer’s front side during the packaging process. The wafer is then attached to a carrier wafer and backgrinded. After bumps are formed on the backside of the wafer, the wafer is diced into units of chips and stacked.

⁵Via middle: A type of TSV that fabricates TSVs after the formation of CMOS but before the metal layers are formed.

To provide a brief overview of the process of forming TSVs with middle vias, transistors such as CMOS are initially fabricated on a wafer during the front-end of line (FEOL) process. Then, using a hard mask (HM)⁶, a pattern is created where the TSV will be formed. Next, the areas without the hard mask are removed through dry etching to create deep trenches. Insulating films, such as oxides, are subsequently deposited via chemical vapor deposition (CVD). This insulating film serves to isolate metals like copper that will later fill the trenches, preventing the metals from contaminating the silicon. Additionally, a thin layer of metal that acts as a barrier is created atop the insulating film.

⁶Hard mask (HM): A mask that creates finer patterns as it is made up of harder materials than soft masks. Since an HM is not photosensitive in itself, additional patterning needs to be formed with the application of photoresist, followed by the subsequent etching process.

This thin layer of metal is used to electroplate copper. After electroplating, the wafer’s surface is smoothed through chemical mechanical polishing (CMP), which simultaneously eliminates all of the copper from the surface of the wafer, ensuring that copper remains solely within the trenches. This is followed by the back-end of line (BEOL) process to complete the wafer fabrication.

▲ Figure 6. The steps of the TSV packaging process (Source: Hanol Publishing)

There are two main types of packages that can be created when producing chip stack packages using TSV technology. The first is a package that uses a substrate with 3D chip stacking technology. The second type involves creating a KGSD and then using it to make a 2.5D or 3D package. The following section will explain the processes of fabricating KGSDs and using them to create 2.5D packages.

As a chip stack package which uses TSV, KGSD has to undergo additional packaging processes such as 2.5D packaging, 3D packaging, and fan-out WLSCP. A prime example of a KGSD product is high bandwidth memory (HBM). Since a KGSD needs to go through additional packaging processes, the connection pins are formed as fine solder bumps rather than conventional solder balls. As a result, while chips in a 3DS package are stacked on a substrate, chips in a KGSD are stacked on a wafer, which also serves as the bottommost chip of the KGSD. In the case of HBM, the chip at the bottom is referred to as the base chip or base wafer, while the chips stacked above it are known as the core chips.

To explain the process steps, bumps are formed on the front surface of both the base and core wafers through a flip chip process. In the context of a 2.5D package, the base wafer necessitates the arrangement of bumps so that they can be attached to interposers. Conversely, the core wafer forms a bump layout that facilitates chip stacking on the front of the wafer. After bumps are formed on the frontside of the wafer, the wafer should be thinned, and bumps should also be formed on the wafer’s backside. However, as previously mentioned during the introduction of the backgrinding process, it is important to note that thinning the wafer can induce the wafer to warp. While conventional packaging makes it possible to have wafers taped to ring frames following the backgrinding to prevent wafer warpage, this method is not viable in TSV packaging where bump formation occurs on the wafer’s backside. This is exactly why the wafer support system (WSS) was developed. Under the WSS, the frontside of the wafer with bumps is bonded to a carrier wafer with a temporary adhesive. At the same time, the backside of the wafer is grinded to thin it. Since it is attached to the carrier wafer, the thinned wafer does not warp.

Additionally, since the carrier wafer is also in the form of a wafer, it can be processed using wafer equipment. Using this structure, bumps are created on the core wafer’s backside. Once bumps are formed on both sides of the core wafer, the carrier is debonded. Then, the wafer is taped to a ring frame and diced in the same manner as conventional packaging processes. The base wafer remains attached to the carrier wafer as it removes chips that are diced from the core wafer to stack on top of the base wafer. When chip stacking is complete, the base wafer is molded while the carrier wafer is debonded. In this way, the base wafer becomes a molded wafer with core chips stacked on it. This wafer is grinded to the target thickness suitable for making a 2.5D package and then diced into chips to form KGSDs. This finished HBM is packed and shipped to customers who will make 2.5D packages.

Wafer Support System (WSS) Process

A WSS refers to a system that allows further processing on the backgrinded surface of a thinned wafer. This process occurs prior to the completed backgrinding process. The WSS process involves two main steps: carrier bonding, which involves attaching a carrier to a wafer for TSV packaging; and carrier debonding, where the carrier is detached after completing processes like forming bumps on the wafer’s backside.

Figure 7 depicts the WSS process steps, where carrier bonding involves applying a temporary adhesive to the wafer before attaching it to the carrier. Carrier debonding involves removing the carrier after processes on the backside are completed and ensuring the wafer is cleaned to remove any residual adhesive.

▲ Figure 7. The steps of the wafer support system (WSS)

There are several considerations to be taken into account in carrier bonding: the overall thickness of the wafers bonded through carrier bonding should be uniform; there should be no voids at the bonded joints; the alignment of the two wafers should be accurate; there should be no adhesive-related contamination at the edge of the wafers; and wafer warpage should be minimized during the process. During the carrier debonding, there should also be: no damage such as chipping⁷ or cracking to the wafer that is separated from the carrier; no adhesive residue; and no deformation of the bumps.

⁷Chipping: The breaking of the edges or corners of a chip or wafer.

Debonding stands out as a relatively complex and critical step within the WSS process. As a result, various debonding methods have been proposed and developed, accompanied by the development of different temporary adhesives for each method. Typical methods include thermal techniques, laser ablation followed by peel-off, chemical dissolution, and chemical cleaning after mechanical lift-off.

Wafer Edge Trimming Process

▲ Figure 8. A comparison of the edges of untrimmed (upper image) and trimmed (lower image) wafers

After a wafer for a TSV package is bonded to a carrier wafer and then backgrinded, it will have sharp edges, as shown in the red circle in the upper image of Figure 8. In this state, the wafer undergoes subsequent processes such as photolithography, metal film formation, and electroplating to form bumps on the backside. However, these processes elevate the risk of chipping the wafer’s edge. Cracks at the edge could propagate inward, eventually rendering further processing impossible, thereby resulting in significant yield loss. To preemptively overcome this problem, the edge of the frontside of the wafer designated for TSV packaging is trimmed and removed before it is bonded with the carrier wafer. When the trimmed wafer is bonded to the carrier wafer and backgrinded, the sharp edge’s prominence diminishes, as shown in the lower part of Figure 8. Consequently, the risk of chipping during subsequent processes is eliminated. The trimming process employs a rotating wafer dicing blade that traverses the wafer’s edge, removing a designated segment of the edge.

Stacking Process

In TSV packaging, the bumps formed on the front and back of wafers are bonded together for stacking. Like in flip chip bonding, mass reflow (MR) and thermocompression are used for bonding. Depending on the type of stacking, the processes are classified as chip-to-chip stacking, chip-to-wafer stacking, and wafer-to-wafer stacking.

When stacking chips with TSVs, micro bumps are used. Therefore, the gaps between these bumps are small, as is the spacing between stacked chips. This is why thermocompression, known for its high reliability, has been widely adopted. However, thermocompression has the disadvantages of taking a long time and has low productivity as heat and pressure must be applied for a certain period during bonding. As such, there’s a growing trend toward adopting MR as an alternative bonding technique.

Looking Beyond the Types of Wafer Packaging

After discussing the two main groups of conventional and wafer-level packages in these two last episodes, the next chapter in our series will delve into the materials that make up the various components of these packages. In particular, it will cover the unique properties of these small materials and analyze how they affect the performances of these semiconductor products.

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The post Semiconductor Back-End Process Episode 8: Exploring the Process Stages of Different Wafer-Level Packages first appeared on SK hynix Newsroom.

In this EE Times article, Ki-ill Moon, the head of PKG Technology Development at SK hynix, covers the evolution of packaging technology and highlights some of the company’s recent efforts and accomplishments in helping to advance the field.

As the speed, density, and functions of a semiconductor product vary depending on how the interconnection is made, interconnection methods during the packaging process are constantly changing and developing as mentioned by Moon in his previous article.

More specifically, the following four types of interconnection techniques have gradually developed over time to eventually provide more efficient and high-quality packaging techniques: wire bonding, flip chip bonding, through-silicon via¹ (TSV) bonding, and hybrid bonding with chiplets.

¹Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

With traditional wire bonding technology advancing all the way to the more recent hybrid bonding with chiplets, unprecedented achievements have been made through improvements in the package’s cost-effectiveness, operating speed, flexibility of chip design, thermal dissipation, and size reduction.

Following such developments, SK hynix developed the world’s first-ever 12-layer HBM3 in April 2023. Furthermore, the company plans to use the most high-powered packaging solution to develop hybrid bonding so it can be applied to its future HBM products such as the 16-layer HBM.

To find out more about the technologies that will help SK hynix elevate its packaging technologies and platform solutions to unprecedented levels, read the full EE Times article here: The Role of Interconnection in the Evolution of Advanced Packaging Technology

The post The Role of Interconnection in the Evolution of Advanced Packaging Technology first appeared on SK hynix Newsroom.

Stacked Packages

Imagine a housing complex consisting of numerous low-rise buildings for thousands of people. It would require a very large area to accommodate the residents. However, the same number of residents could fit in a single skyscraper. This example clearly shows one of the key benefits of stacked packages. Compared to a product made with multiple packages spread horizontally across a wide area, a product consisting of stacked packages offers enhanced performance within a much smaller space. In addition to being an important packaging technology, stacked packaging is also an essential method in product development.

It used to be common for products to have only one chip per package, but it is now possible to develop a multi-chip package that has different functions or to place multiple memory chips in a single package that has an increased capacity. Furthermore, the development of SiP has allowed various system components to be implemented in a single package. Such technologies have enabled semiconductor companies to create high value-added products while also responding to the diverse needs of the market.

▲ Figure 1. Different methods of stacking packages (Source: Hanol Publishing)

As Figure 1 shows, stacked packages are categorized into three major types based on their distinct development techniques: 1) package stacks that are made by vertically stacking the packages, 2) chip stack packages that use wire bonding to stack chips within a single package, and 3) chip stack packages that use through-silicon via (TSV)¹ rather than traditional wire bonding for the internal electrical interconnections. Each of these stacked packages has different features and various advantages and limitations which will determine their future applications.

¹Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

#1. Package Stacks

A package stack is made by vertically stacking the packages. Consequently, its advantages and disadvantages are opposite to that of chip stack packages. The package stack method places packages on top of each other once they have completed testing, so it is possible to easily replace a package that fails a test with a properly functioning package. This, in turn, results in better test yields compared to chip stack packages. However, due to package stacks’ larger size and longer signal paths, their electrical characteristics can be inferior to that of chip stack packages.

One of the most common package stacking methods is package-on-package (PoP), which is widely used in mobile devices. For a PoP in a mobile device, the types and functions of the chips used in the upper and lower packages may vary while the chip manufacturers can also differ.

In general, the upper packages mainly include memory chips made by semiconductor memory companies while the packages stacked below feature chips with a mobile processor that are designed by fabless companies and produced in foundries and Outsourced Semiconductor Assembly and Test (OSAT) facilities. As the packages are manufactured by different parties, quality testing is conducted before being stacked. Even if a defect occurs after stacking, it can be reworked by just replacing the defective part with a new package. Accordingly, it is clear that the mobile business sees significant benefits from package stacking.

#2. Chip Stacks with Wire Bonding

When placing multiple chips in a package, they can either be stacked vertically or attached horizontally to the board. Given that the horizontal layout may result in a larger package size, vertical stacking has become the preferred method. Compared to package stacks, chip stack packages are smaller in size and possess enhanced electrical characteristics due to their shorter electrical signal paths. However, even if a defect is found in a single chip during testing, the entire package needs to be discarded. Thus, chip stack packages have relatively low test yield rates.

In chip stack packages, the memory capacity increases as more chips are stacked in the package. This has resulted in the development of technologies which enable more chips to be layered in a package. However, as it is undesirable for the package to get thicker even as more chips are stacked, technologies that limit the package’s thickness have been under development. To do so, everything that affects the thickness of a package including the chip and the substrate must be made thinner, and the gap between the uppermost chip and the surface above the package needs to be reduced. This poses many challenges in the packaging process because chips are more likely to get damaged as they become thinner. That is why developments in packaging processes are underway to overcome these challenges.

#3. Chip Stacks with TSV

TSV is a chip stacking technique that drills holes through silicon to accommodate electrodes. Instead of using the traditional method of wiring to connect chip-to-chip or chip-to-substrate, TSV connects chips vertically by drilling holes in the chip and filling them with conductive materials such as metal. Although a chip-level process is used when stacking with TSV, a wafer-level process is used to form TSV and solder bumps on the front and back of the chip. Therefore, TSV is classified as a wafer-level package technology.

▲ Figure 2. A cross-sectional view of a chip which applied TSV technology (Source: Hanol Publishing)

The main advantages of packages using TSV are the high level of performance and smaller package size. As shown in Figure 2, the chip stack package with wire bonding has wires connected to the sides of each stacked chip. As there are more stacked chips and connected pins, the wiring becomes more complex, with more space needed to connect them. In contrast, the chip stack with TSV does not require complicated wiring and, therefore, allows reduction in package size.

As explained in the previous episode, flip chips have good electrical properties due to several reasons: it is easier to form I/O pins in desired locations, there is an increase in the number of pins, and they have short electrical signal transmission paths. These are the same reasons that give TSV packages strong electrical properties. When sending an electrical signal from a chip to the chip right below it, TSV allows the signal to go straight down. In contrast, if wire bonding is used, the signal transmission path becomes much longer as the signal has to go down to the substrate before making its way up to the chip. As shown in the image of a chip stack with wiring in Figure 2, wiring connections cannot be made in the center of the chip. Contrastingly, TSV packages allow the center of the chip to be drilled, made into electrodes, and connected with other chips. Unlike wiring connections, TSV enables the number of pins to be significantly increased.

High Bandwidth Memory (HBM) utilizes a new DRAM architecture that takes advantage of this ability to increase the number of pins. Typically, an “X4” in DRAM specification implies that there are four pins that can send information, or 4 bits of information can be simultaneously sent from the DRAM. Accordingly, X8 refers to 8 bits, X16 refers to 16 bits, and so on. It is favorable to increase the number of these pins as it allows more information to be sent simultaneously. However, chip stacking with wiring could only reach X32 due to limitations, while stacking through TSV does not have such limitations, enabling HBM to go up to X1,024.

Current mass-produced memory products that apply TSV to DRAM include HBM and 3D stacked memory (3DS). The former is used in graphics, networking, and high-performance computing (HPC) applications, while the latter is primarily used as a DRAM memory module.

▲ Figure 3. A 2.5D package using HBM (Source: Hanol Publishing)

Rather than being a fully packaged product, HBM is a semi-packaged product. When an HBM product is sent to a system semiconductor manufacturer, they use an interposer² to make a 2.5D package³, with an HBM placed side-by-side to a logic chip as shown in Figure 3. Since substrates in 2.5D packages are unable to provide pads that can support all the I/O pins of both HBMs and logic chips, interposers come in to accommodate HBMs and logic chips by creating pads and metal wiring. Then, these interposers connect back with the substrate. As for these 2.5D packages, they are considered as a type of SiP.

3DS memory, another product that uses TSV, is a type of memory module with a BGA⁴ package mounted on a PCB board. Although DRAM memory modules in servers require high speed and a large capacity, chip stack packages that use wiring are unable to meet these requirements due to their speed limitations. This has led to the use of modules made from TSV-applied chip stack packages for high-end systems such as servers.

²Interposer: Wide and extremely fast electrical signal conduits used between die in a 2.5D configuration.

³2.5D package: 2.5D and 3D packages include multiple integrated circuits inside each package. In the 2.5D structure, two or more active semiconductor chips are placed side-by-side on a silicon interposer. In the 3D structure, active chips are integrated by die stacking vertically.

⁴Ball grid array (BGA): A type of surface mount chip package that uses a grid of solder balls as its connectors.

System-In-Package (SiP)

A package consisting of HBM and a logic chip is a type of SiP. As its name suggests, SiP implements a system in a single package. While components such as sensors, analog-to-digital (A/D) converters, logic chips, memory chips, batteries, and antennas must also be included to form a complete system, it is not possible to include all these system components into a single package with the current developments in technology. It has therefore become the goal of researchers to continue developing package technologies in this area, and SiPs today usually refer to combining some of the system components in a single package. For instance, packages that have applied HBM combine HBM and the logic chip into a single package to create an SiP.

Unlike SiP, system-on-chip (SoC) implements system functions on the chip-level. In other words, several system functions are implemented on one chip. As an example, most processors today have static RAM (SRAM) memory within the chip, allowing the logic functions of the processor and the memory functions of the SRAM to be implemented together on a single chip. Therefore, these processors are classified as an SoC.

SoCs have a complex and lengthy development process because they require multiple functions to be packed into a single chip. Moreover, upgrading the functions of a single element in an already developed SoCs requires one to design and develop them from scratch. SiPs, on the other hand, are easier and quicker to develop because they are made by collecting already developed chips and devices into a single package. Even if the device has a completely different structure, the chip itself is developed and manufactured separately, making it relatively easy to make it into a single package. Also, if just a single aspect of the function needs an upgrade, the newly developed device can be implemented in the chip without developing the whole package from scratch. However, if a product is going to be used in large quantities over an extended period of time, it may be more efficient to develop it as an SoC rather than an SiP as the latter requires more materials to be manufactured and leads to a larger package size to fit multiple chips in a single package.

Despite the various differences between SoCs and SiPs, it is not necessary to choose between one of these two technologies. In fact, they can be combined to create synergies. Once an SoC is developed, it can be packaged with other functional chips into a single package and implemented as an enhanced SiP.

▲ Figure 4. Comparison of signal transmission path length of SoC and SiP stacked with TSV (Source: Hanol Publishing)

When comparing the performance of SiPs and SoCs, it was originally thought that the electrical characteristics of SoCs were better due to their implementation on a single chip. However, with the advent of chip stacking technology such as TSV, SiPs can have electrical characteristics that are on par with SoCs. Figure 4 shows a comparison of the signal transmission paths of SoCs and SiPs stacked with TSV. When a signal is transmitted from one end of an SoC chip to the opposite corner, the path is much shorter if the SoC is divided into nine parts and stacked with TSV.

▲ Figure 5. Conceptual diagram of a chiplet

In addition to a focus on the various advantages of SiPs stacked with TSV, a technology called chiplets has gained a lot of attention recently. As shown in Figure 5, it is a technology that divides existing logic chips by function and connects them with TSV. Chiplets have three main advantages over monolithic chips.

First, the chiplets offer a yield improvement over monolithic chips. The wafer yield is limited if the size of a single chip on the wafer is big, but making the chips smaller can increase wafer yield and thus reduce manufacturing costs. Take the example of a 300 mm wafer cut into 100 or 1,000 chips (net die). If the wafer process causes five chips to fail because five impurities are evenly distributed across the front of the wafer, the product with 100 chips has a yield of 95% and the product with 1,000 chips has a yield of 99.5%. The yield is therefore much higher for products with more net dies, or with a smaller chip size. Therefore, it is more cost-effective to cut up a chip by functions and implement it as SiP rather than as a single chip through SoC.

The second advantage is streamlined development. With a single chip, the entire chip needs to be redeveloped in order to upgrade its functionality or apply the latest technology. However, dividing the chips can shorten the development period and make the process more efficient as only the chip with the relevant function needs to be upgraded or developed with the latest technology. For example, some of the segmented chips use the existing 20 nanometer (nm) technology, while others use the latest sub-10 nm technology to increase development efficiency.

The third benefit is the centralization of technological development. By dividing chips by function, it is not necessary to develop a chip for every function. Only the chips used for the core technology need to be developed, and everything else can be purchased or outsourced so companies can focus on developing their own core technologies.

Thanks to these advantages, major semiconductor companies are introducing chiplet-based semiconductor products or have added them to their roadmaps.

Following the previous episode that looked into the various conventional and wafer-level packaging technologies, we finished the roundup of packaging technologies and their distinct characteristics. While stacked packages and SiPs have come a long way in their development, semiconductor researchers will continue efforts to enhance the capability of these high-quality technologies with numerous functions that take up a minimal amount of space. These efforts are expected to increase the efficiency of the packaging process as a whole through the production of packages with advantages in size, functionality, and performance.

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The post Semiconductor Back-End Process Episode 4: Understanding the Different Types of Semiconductor Packages, Part 2 first appeared on SK hynix Newsroom.

• Develops HBM3 product with industry’s largest 24GB memory capacity; customers’ performance evaluation of samples underway
• Features high-capacity and high-performance through stacking of 12 DRAM chips
• Plans to complete preparation for mass production by first half of 2023, aimed at solidifying company’s leadership in cutting-edge DRAM market

Seoul, April 20, 2023

SK hynix Inc. (or “the company”, www.skhynix.com) announced today it has become the industry’s first to develop 12-layer HBM3¹ product with a 24 gigabyte (GB)² memory capacity, currently the largest in the industry, and said customers’ performance evaluation of samples is underway.

¹HBM (High Bandwidth Memory): A high-value, high-performance memory that vertically interconnects multiple DRAM chips and dramatically increases data processing speed in comparison to traditional DRAM products. HBM3 is the 4^th generation product, succeeding the previous generations HBM, HBM2 and HBM2E

²Maximum memory capacity of the previously developed 8-layer HBM3 product was 16GB

“The company succeeded in developing the 24GB package product that increased the memory capacity by 50% from the previous product, following the mass production of the world’s first HBM3 in June last year,” SK hynix said. “We will be able to supply the new products to the market from the second half of the year, in line with growing demand for premium memory products driven by the AI-powered chatbot industry.”

SK hynix engineers improved process efficiency and performance stability by applying Advanced Mass Reflow Molded Underfill (MR-MUF)³ technology to the latest product, while Through Silicon Via (TSV)⁴ technology reduced the thickness of a single DRAM chip by 40%, achieving the same stack height level as the 16GB product.

³MR-MUF (Mass Reflow Molded Underfill): A method of placing multiple chips on the lower substrate and bonding them at once through reflow, and then simultaneously filling the gap between the chips or between the chip and the substrate with a mold material.

⁴TSV (Through Silicon Via): An interconnecting technology used in advanced packaging that links the upper and lower chips with electrode that vertically passes through thousands of fine holes on DRAM chips. SK hynix’s HBM3 that integrated this technology can process up to 819GB per second, meaning that 163 FHD (Full-HD) movies can be transmitted in a single second.

The HBM, first developed by SK hynix in 2013, has drawn broad attention from the memory chip industry for its crucial role in implementing generative AI that operates in high-performance computing (HPC) systems.

The latest HBM3 standard, in particular, is considered the optimal product for rapid processing of large volumes of data, and therefore its adoption by major global tech companies is on the rise.

SK hynix has provided samples of its 24GB HBM3 product to multiple customers that have expressed great expectation for the latest product, while the performance evaluation of the product is in progress.

“AI models continue to grow and drive demand for large memory capacity,” said Roman Kyrychynskyi, CVP Product Management at AMD. “We welcome the efforts by our memory suppliers to increase HBM memory capacity to support cutting edge AI models.”

“SK hynix was able to continuously develop a series of ultra-high speed and high capacity HBM products through its leading technologies used in the back-end process,” said Sang Hoo Hong, Head of Package & Test at SK hynix. “The company plans to complete mass production preparation for the new product within the first half of the year to further solidify its leadership in cutting-edge DRAM market in the era of AI.”

About SK hynix Inc.

SK hynix Inc., headquartered in Korea, is the world’s top tier semiconductor supplier offering Dynamic Random Access Memory chips (“DRAM”), flash memory chips (“NAND flash”) and CMOS Image Sensors (“CIS”) for a wide range of distinguished customers globally. The Company’s shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxembourg Stock Exchange. Further information about SK hynix is available at www.skhynix.com, news.skhynix.com.

Media Contact

SK hynix Inc.
Global Public Relations

Technical Leader
Joori Roh
E-Mail: global_newsroom@skhynix.com

Technical Leader
Kanga Kong
E-Mail: global_newsroom@skhynix.com

The post SK hynix Develops Industry’s First 12-Layer HBM3, Provides Samples to Customers first appeared on SK hynix Newsroom.

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With the opening of the 4th industrial revolution era and the spread of high technologies such as artificial intelligence (AI), 5G, and autonomous driving, the demand for high-performance and ultra-small semiconductors is exploding. Accordingly, “packaging” technology, where semiconductors become solutions to have the best performance and create high added value, is now drawing great attention.

Along with this trend, SK hynix is also focusing on securing future competitiveness by paying attention to the packaging business through active investment and continuous technology development. This time, the newsroom team met with Seung Taek Yang, KI-ILL Moon, Jinwoo Park, and Ho-Young Son – Project Leader (PL) of the SK hynix’s PKG Development Division to hear about the present and the future of SK hynix’s packaging technology including conventional package, Through-Silicon Via (TSV), and Fan-Out Wafer-Level Package (FO-WLP).

Packaging Technology Determines Future Competitiveness as the Key to Increasing the Memory Product Value

After the front-end process where circuits are formed on a wafer, semiconductor chips go through the back-end process consisting of a packaging process and a test. Although a number of fine electric circuits are integrated on a chip, the chip itself cannot perform the role of a semiconductor. The packaging process serves to connect a chip electrically to the outside so that the chip can function properly and protect it from the external environment. Also, another role of packaging is to control heat generation to ensure efficient thermal emission by semiconductors.

With the advancement of semiconductor technology which makes semiconductor products faster and more functional, thermal problems are becoming more and more serious, resulting in the greater importance of the thermal dissipation of semiconductor packages. Also, even if the chip speed is high, as the electrical connection path to the system is made during the packaging process, packaging should also be implemented at a high speed to respond to the faster chip speed. For this reason, cutting-edge packaging technology for the high-density, high-speed, low-power, small-from-factor, and high-reliability semiconductor market is crucial.

Seung Taek Yang PL

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“Packaging technology is very important for high-performance devices to perform properly. For example, to transmit and receive a large amount of data at once, numerous electric paths connected to the outside should be formed, and what plays this role is the packaging process. Packaging technology stacks multiple chips to implement a capacity of four times, 16 times, or even more compared to the conventional chips, or combines several types of chips to create a system. In other words, depending on the packaging technology, the added value of a product can highly increase. Now, it is an era where chip technology alone cannot preoccupy the future market dominance without advances in packaging technology.”

SK hynix’s Packaging Technology, How Has It Developed?

As mentioned above, semiconductor packaging plays various roles including mechanical protection, electrical connection, mechanical connection, and thermal dissipation. In detail, during the packaging process, semiconductor chips are wrapped with a packaging material such as an Epoxy Molding Compound (EMC)¹ to protect them from external mechanical and chemical impacts. In addition, the packaging process physically or electrically connects the chips to a system to supply power to operate chips, ensures input and output of signals to perform desired functions, and allows dissipation of heat generated when semiconductor products are operated.

The methods of packaging semiconductors can be largely divided into two types. One is the conventional package, which is a traditional method of applying a packaging process to individual chips separated from wafers. The other is the Wafer-Level Package (WLP), where part or all of the process is carried out at the wafer stage and later cut into single pieces.

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In the packaging field as well, SK hynix has continuously developed and created innovative products from the past to the present. The early packaging technology used in 1986, when DRAM development and production began in earnest, was the lead frame² method that connects chips and pads by using gold wires. Soon after, however, the lead frame structure faced its limit, with the improvement in the device performance. Accordingly, other structures such as the Fine-Pitch Ball Grid Array (FBGA)³ based on a substrate are applied. This type of package is a conventional package, which is mainly applied to high-density NAND or mobile DRAM products since it can stack many chips in a package.

Since then, to meet the high-performance specifications required for memory products, the existing method of the conventional package has been developed and the new method of WLP has begun to be introduced, resulting in two paths of the development of the packaging technology. In particular, WLP technology is suitable for realizing high-performance products. Since packaging in the same size as the chip is possible when using this technology, it can minimize the size of finished semiconductor products. Also, saving cost is another advantage of this technology as it does not require materials such as substrates or wires.

From 2007, SK hynix has introduced the flip chip⁴ process, a technology that combines conventional packaging and WLP in graphics DRAM that requires high performance, while applying the Redistribution Layer (RDL)⁵ process to the main memory. From 2007 to 2010, SK hynix revealed a series of memory modules to which the Wafer-Level Chip Scale Package (WLCSP)⁶ was applied for the first time in the world. Based on this technology, the company applied the 3-Dimensional Stack (3DS)⁷ and introduced a 128 GB DRAM module.

More recently, the WLP process is mainly used for products such as High Bandwidth Memory (HBM), which needs to satisfy the needs for high density and high performance, and Computing DRAM, which requires much more capacity than existing products.

In 2013, SK hynix succeeded in developing and mass-producing HBM with TSV structure for the first time in the world and mass-produced 3DS products developed for High-Density products. In 2019, the company developed HBM2E and succeeded in mass-producing it just in 10 months, preoccupying a clear advantage in the HBM market and maintaining it until now.

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Next-Generation Packaging Technology as a Growth Source of SK hynix

With the increase in the demand for high-performance and ultra-small semiconductors, packaging technology is emerging as a core technology for the next-generation semiconductors to enhance semiconductor performance and production efficiency. Accordingly, SK hynix is actively developing innovative technologies to raise the value of memory solutions by strengthening the packaging competitiveness in the fields of the conventional package, TSV, and FO-WLP.

▶ “Conventional Package” through a Total Solution of Materials, Processes, and Equipment

For a single package to implement High Density, the key is to stack chips as thin as possible, which requires high-level element technologies. In this regard, KI ILL Moon PL explained the SK hynix’s technology level by presenting an index of “chip stack count”.

KI ILL Moon PL

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“SK hynix’s packaging technology is the highest level in the industry. In the case of mobile DRAM, 16 GB is achieved by integrating 16 units of 8 Gb memory in one package. In the case of NAND, a product in which 16 layers are stacked in a package is mass-produced. In addition, SK hynix is in the process of securing element technology to apply 32-layer stacking technology to mass-produced products for the first time in the industry.”

What is the competitiveness unique to SK hynix, especially in the conventional package stage to survive in the increasingly fierce competition for miniaturization and stacking? Currently, SK hynix is preparing various solutions to maximize the performance required for each characteristic of memory products.

In computing and graphics memory, the power control function is crucial as well as high speed. To achieve this, SK hynix is preparing thermal dissipation solutions for easier power control. In terms of materials and structures, the company is developing various solutions including thermal dissipation EMC and Exposed Mold Package. Also, in the case of mobile memory where the speed determines its competitiveness, wire bonding technology is being developed to reduce signal delay or capacity.

In NAND, the complex solution of the combination of controller and DRAM determines the competitiveness. For this reason, SK hynix is developing element technologies in advance so that they can be used as needed to ensure a timely supply of various solutions to customers.

As the performance of electronic products evolves, the required level for semiconductors continues to increase as well. How can SK hynix overcome the limitations in the future? Moon PL said, “Every moment, we have been facing a limit and even now, we are facing one. However, we always have been overcoming the limit, like we are now.”

For instance, just a few years ago, it was considered impossible to reduce the chip thickness below 50 ㎛ to stack eight DRAMs. Now, however, it has become a very common technology. Moon PL said, “The reason we could overcome the limit at that time was the development of the equipment, processes, and materials that could handle thin dies. We will continue to take the lead in overcoming the limits in the future through various efforts such as boundless cooperation encompassing different functions of materials, processes, and equipment in the packaging field and seeking for a total solution.”

▶ “TSV” for Realizing High-Performance and High-Density Memory

To become a winner in the ultra-speed memory HBM market, a technology gap with competitors should be widened, going beyond the level of customer demand. To achieve this, the PKG Development Division developed an exclusive, specialized technology called Mass Reflow Molded Underfill (MR-MUF)⁸ for the first time in the world and applied it to HBM products. Based on this technology, the thermal dissipation performance has been improved by more than 10℃ compared to competitors.

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Meanwhile, TSV technology was the key to the innovative enhancement in the processing speed of HBM2E, “the world’s fastest DRAM”. SK hynix has implemented 16 GB, which is more than double compared to the previous generation by connecting eight 16 Gb DRAM chips vertically with the TSV technology. TSV is one of the WLP technologies that SK hynix is currently focusing on, and SK hynix has the highest level of TSV competitiveness in the industry.

Jinwoo Park PL

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“SK hynix has secured element technologies essential for stably handling thin wafers and stacking thin chips. We have developed the Advanced Mass Reflow method, which can stack 30㎛-thick chips in multiple layers as of today. Another competitiveness of SK hynix is the organizational power to ‘realize what we need to do’ rather than ‘realize what we can do’, based on the experience of succeeding in the HBM2E development. Our differentiated competitiveness is the process of collaborating between members and seeking a solution together even in difficult situations.”

In addition to the HBM2E, 3DS products are also one of the examples of innovation in TSV technology. Previously, the Mass Reflow (MR)⁹ process commonly used in the flip chip method had been converted to the Thermal Compression (TC)¹⁰ process for multi-layer stacking and miniaturization, but it has reached the limit of productivity. To overcome this, SK hynix applied the MR method to 3DS for the first time in the world, enabling stable production and quality control. This product is expected to be even more highly favored in the near future, since the DDR5 high-density market will be completely converted to 3DS.

SK hynix’s goal this year is to increase the TSV product line and secure profitability. To achieve this goal, company-wide efforts are being made.

Park PL said, “The core of the TSV technology is to implement stacking in a stable structure, quickly and cost-effectively. The TSV technology is applied only to HBM and 3DS products currently, but this can be extended and applied to mobile and NAND products, when high processing speed is needed. In preparation for this, we are working hard in collaboration with many other departments to proactively secure cost competitiveness.

▶ “FO-WLP”, a Packaging Technology of the Next Generation

In addition to the flagship packaging technology, SK hynix is focusing on the “Fan-Out Wafer-Level Package (FO-WLP)” as a growth source and a technology to contribute to profit generation in the future.

Wafer-Level Chip Scale Package (WLCSP) can be divided into Fan-In Wafer-Level Package (FI-WLP) and Fan-Out Wafer-Level Package (FO-WLP). Both technologies adopt a method of packaging by attaching solder balls (I/O terminals) directly onto the chip without a medium such as a substrate. As the length of wiring is reduced, the electrical characteristics are improved, and more chips can be stacked by reducing the package thickness.

Here, the “fan” refers to the chip size. When the chip size is the same as the package size and the solder balls for packages are implemented within the chip size, it is called “fan-in”. When the package size is larger than the chip size and the solder balls are implemented outside the chip as well, it is called “fan-out”.

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In the case of FI-WLP, where the chip size is just same as the package size, it has a disadvantage of having to establish a new package infrastructure when a new chip is developed, since a new chip requires a different package size even though it has the same function as the previous one. In addition, if the size of the package solder ball arrangement is larger than the chip size, the package cannot be made. It is also inefficient in that defective chips should be packaged as well, since the wafer is cut after the packaging process is completed. On the contrary, in the case of FO-WLP, there is no need to package defective chips because chips are cut first before the process. Since the package size can be adjusted, it is possible to use the existing package test infrastructure and it is easy to implement the desired package solder ball arrangement. Especially, it is advantageous in that different chips can be mounted in a single package as horizontal connection with heterogeneous chips is possible.

Ho-Young Son PL

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“FO-WLP is mainly used for packaging at least two heterogeneous devices such as packaging different System on a Chip (SoC) dies or packaging an SoC and a memory chip together. It is considered a next-generation packaging technology that will satisfy the demand for high-performance products. For this reason, many foundry companies are jumping into the back-end process technology development and expanding the market based on high technology and solid business models. SK hynix is also strengthening its investments in infrastructure related to FO-WLP technology, aiming for the company’s mid to long-term growth. Also, SK hynix is steadily preparing for the application of the FO-WLP technology for each memory application, as well as developing element technologies step by step to implement products.”

Currently, SK hynix is priorly reviewing adopting the FO-WLP to memory products. It is expected that it will significantly improve the package size and device characteristics by eliminating the need to use substrate while stacking multiple, identical chips. This will be also useful to implement a package structure that dramatically improves the performance limit of the current DRAM. Ultimately, it is expected to accelerate the development of direct packaging technology for heterogeneous devices such as memory and SoC and facilitate active participation in the semiconductor ecosystem environment.

Meanwhile, Son PL emphasized the necessity of understanding the memory system better than anything else. Based on the understanding, especially on the limitations of the current memory devices, it is important to find a solution through close cooperation between related departments to overcome such limitations, Son PL said.

In addition, he showed the determination to lead the semiconductor market in the new path based on the next-generation packaging technology.

He said, “HBM products were developed by SK hynix for the first time in the world eight years ago, and have been advanced through many trials and errors. Only recently, they have become technologically competitive and started to contribute to financial achievements. Looking back to this, you can see that it takes a long time for new technology to be adopted in the market and contribute to generating profits. This also means that if we do not prepare for the future from this moment, we will not be able to survive the rapidly changing semiconductor competition.”

Lastly, he expressed his confidence in SK hynix’s future, by saying, “We believe that we will be able to lead the market with competitive technologies if we continue to carefully prepare new technologies step by step without limiting ourselves. A number of members from various related departments, not only the PKG Development Division, are working hard together, so you can look forward to the future of SK hynix.”

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Based on the technological prowess and the experience of success that have been solidly accumulated over time, the PKG Development Division overcomes limitations and is moving toward the next step. The four PKG Development leaders, who undertake a key mission to strengthen SK hynix’s future competitiveness, delivered a message of their ambition to stakeholders.

“In the current environment, we cannot survive with the device development alone. Our way forward is to develop products that meet customers’ need in a timely manner through collaboration between the device and packaging fields. Also, even with the same product, we will need to constantly study strategies for securing differentiated advantages compared to our competitors. In that sense, we expect that packaging will play a key role. To lead the packaging field, numerous members of SK hynix are working hard even at this moment in various areas from technology development to cost reduction and customer response. You can look forward to the SK hynix’s future!”

Articles related to packaging technology

SK hynix CEO Seok-Hee Lee Talks about the Future of Semiconductor Memory and SK hynix’s Management Strategy
https://news.skhynix.com/sk-hynix-ceo-seok-hee-lee-talks-about-the-future-of-memory-semiconductor-and-sk-hynixs-management-strategy/

[Top TL] P&T Enhances the Value of Memory Solutions: Sang Hoo Hong, Head of P&T
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¹Epoxy molding compound (EMC): Thermosetting plastic with excellent mechanical and electrical insulation and temperature resistance characteristics, as a resin with relatively low molecular weight, capable of three-dimensional curing in the presence of a hardener or catalyst
²Lead frame: A lead refers to a line that comes out of an electronic circuit or a terminal of an electric component and is used to connect an electronic component to a circuit board. Lead frame refers to a shaped metal plate of an inner/outer lead used when assembling a semiconductor chip; as a thin metal plate that attaches chips cut from a wafer, leads, etc. to be used in a package are formed.
³Fine-Pitch Ball Grid Array (FBGA): As a substrate type package, a package in which a pin that serves as an electrical and mechanical connection between the package and PCB is formed of a ball-shaped solder ball is called a Ball Grid Array (BGA). Among the BGA, a package with solder balls in a small distance is called FBGA, by attaching “fine” to BGA.
⁴Flip Chip: An interconnection technology where bumps are formed on a chip’s bond pad, flipped over, and bonded to a board such as a substrate; compared to wire bonding, which is a technology that electrically connects the top of a chip and a substrate or lead frame with wires by using heat and ultrasonic waves, the mounting area and height can be reduced and the electrical characteristics can be improved.
⁵Redistribution layer (RDL): A generic term for technologies that form a metal wiring layer using the wafer-level package process method and change the position of the existing chip pad to the desired position
⁶Wafer-Level Chip Scale Package (WLCSP): Unlike conventional packaging technology, where packaging is done by cutting a wafer into chip units after the fab process is completed at the wafer level, wafer-level packaging is done as a wafer-level process rather than a chip-level process and produces a single piece of the product.
⁷3D-Dimensional Stack (3DS): In a broad sense, it refers to a package where at least two IC chips are vertically stacked. More specifically, however, it refers to a package where the inside of stacked DRAM chips is electrically connected by using TSV. 3DS memory is made into a BGA package, which is then mounted on a PCB to make a product in the form of a memory module.
⁸Mass Reflow Molded Underfill (MR-MUF): A molding compounding process that secures gap filling in the flip chip process, while performing molding at the same time
⁹Mass reflow (MR): A process where multiple devices are aligned and placed on a substrate and heated in an oven, etc., to melt solders to bond them altogether; since it is carried out all at once, the word “mass” is used in this term.
¹⁰Thermal compression (TC): A method of bonding by applying heat and pressure to the junction where flip chip bonding is performed

The post Packaging Technology, a Key to Next-Generation Semiconductor Competitiveness, How Far Has SK hynix Come? first appeared on SK hynix Newsroom.