Photoresists (PR): Sensitizers, Resins, & Solvents Create Patterns & Barriers

Photoresists are compounds formed from melting soluble polymers and photosensitive materials—which undergo a chemical reaction such as degradation or fusion when exposed to light energy—in a solvent. They are used to create the intended pattern during photolithography in WLP, while they also serve as a barrier by plating metal wiring during the subsequent electroplating¹ process. The materials that make up a photoresist can be found below in Figure 1.

¹Electroplating: A reaction where oxidation occurs at the positive plate to produce electrons which are transmitted to a wafer with a solution that has metal ions. These metal ions are negative plates that become metal.

▲ Figure 1. The components and roles of photoresists (Source: Hanol Publishing)

A photoresist is classified as positive or negative depending on how it responds to light. In a positive photoresist, the areas exposed to light undergo degradation which weakens the bonding, while unexposed areas experience cross-linking² that strengthens the bonds. Therefore, areas that have received light are removed during the development process. However, in the case of negative photoresists, the areas that are exposed to light experience cross-linking and harden, leading them to remain intact while unexposed areas are removed. As negative photoresists can be applied more thickly during the spin coating process as they tend to have a higher viscosity than positive photoresists, they are usually used when forming higher solder bumps. On the other hand, positive photoresists need to be applied at least two times.

The light used during photolithography can be classified according to its wavelength, which is measured in nanometers (nm). Light with shorter wavelengths has been used during photolithography to form finer patterns for semiconductors that have gone through scaling, leading to the enhancement of photoresists. Accordingly, photoactive compounds (PAC) are used for g-line³ and i-line⁴ photoresists with longer wavelengths, while chemically amplified resists (CAR)⁵ are used for photoresists with shorter wavelengths. As for WLPs, they typically use i-line steppers⁶.

²Cross-link: A chemical reaction that links polymer chains through chemical bonds.
³g-line: A line of the mercury spectrum corresponding to a wavelength of about 436 nm.
⁴i-line: A line of the mercury spectrum corresponding to a wavelength of about 356 nm.
⁵Chemically amplified resists (CAR): A resist used to improve the photosensitivity of photoresist materials.
⁶Stepper: Equipment used to expose wafers. Different types of equipment are used for wafer exposure with varying degrees of accuracy depending on the type of light used.

Plating Solutions: Metal Ions, Acids, & Additives For Controlled Electroplating

Plating solutions are used during electroplating. These solutions are comprised of metal ions to be plated during the electroplating process, acids that become solvents to dissolve metal ions in the solutions, and various additives that enhance the properties of the plating solution and plating layer. Some metals that can be plated during the electroplating process include nickel, gold, copper, tin, and tin/silver alloy. These metals exist as ions inside the plating solution. For solvents, some commonly used acids include sulfuric acid and methanesulfonic acid. Meanwhile, the additives include levelers which limit the buildup of materials and flatten the surface of the plating layer, and grain refiners that prevent the lateral growth of plating grains so they become finer as they grow.

▲ Figure 2. The roles of plating solution additives (Source: Hanol Publishing)

Photoresist Strippers: Using Solvents to Remove Without a Trace

After the plating process is finished, the photoresist needs to be removed with a photoresist stripper without chemically damaging the wafer or leaving any residue. Figure 3 shows this process of removing a photoresist. First, the solvent of the photoresist stripper reacts when it contacts the photoresist surface, which starts to swell up. Then, the alkaline stripper breaks down and dissolves the swollen photoresist surface.

▲ Figure 3. The sequence of a photoresist stripper removing a photoresist (Source: Hanol Publishing)

Etchants: Using Acids, Hydrogen Peroxide & More to Precisely Dissolve Metals

WLP requires a sputtering⁷ process to create a seed layer, a thin layer of sputtered or evaporated metal, for electroplating. This seed layer needs to be dissolved with an acid etchant after the completion of plating and photoresist stripping.

Figure 4 displays the primary components and roles of etchants. Depending on the metal to dissolve, copper etchants, titanium etchants, silver etchants, and other etchants are used. Such etchants should possess etch selectivity—the capability to selectively dissolve certain metals while leaving others undissolved or just slightly dissolved. They also should have a high etch rate to enhance the process efficiency, as well as process uniformity which enables the etchant to dissolve the metal at a uniform rate regardless of the metal’s location on the wafer.

⁷Sputtering: A type of physical vapor deposition (PVD) in which high-energy ions are bombarded against a metal target, enabling the ejected metal ions to be deposited onto the wafer surface.

▲ Figure 4. The main components and roles of etchants (Source: Hanol Publishing)

Sputtering Targets: Depositing Metal Onto a Substrate

A sputtering target is used as a material when a thin metal film is deposited on a wafer with the sputtering method during the physical vapor deposition (PVD)⁸ process. Figure 5 shows the process of how this target is fabricated. A cylinder is created using raw materials which have the same composition as the metal layer that is going to be sputtered, and then it is forged, pressed, heated treated, and finally shaped into a target.

⁸Physical vapor deposition (PVD): As one of the ways to deposit thin films, PVD physically separates and deposits a material on a surface.

▲ Figure 5. The process of fabricating a sputtering target (Source: Hanol Publishing)

Underfills: Filling Holes With EMC, Pastes, & Film for Joint Protection

Underfills enhance joint reliability by filling spaces between the substrate and the chip or between chips that are connected by bumps just as in flip chip bonding. There are two main underfill processes that fill up the spaces between bumps. Post-filling fills the space between bumps after flip chip bonding, while pre-applied underfill fills the material before it. Furthermore, post-filling is further divided into capillary⁹ underfill (CUF) and molded underfill (MUF). After flip chip bonding is applied, CUF fills in the gaps between bumps by using a capillary to inject underfill material into the side of the chip. This adds surface tension within the gap between the chip and the substrate. As for MUF, it allows epoxy molding compound (EMC)¹⁰ to function as an underfill during molding and simplifies the process.

⁹Capillary: A very thin tube used to transfer the liquid encapsulant material into the semiconductor package.
¹⁰Epoxy Molding Compound (EMC): A composite of inorganic silica and a thermosetting epoxy polymeric material that creates three-dimensional bonds when heated.

During the pre-applied underfill process, the underfill is applied differently based on whether it is carried out at the chip level or at the wafer level. For the chip level, different processes and materials are used depending on whether the joints are filled with non-conductive paste (NCP) or non-conductive film (NCF). For the wafer level, NCF is primarily used as the underfill. Figure 6 shows the types of materials used for underfill and the relevant processes.

▲ Figure 6. The different types of underfill processes (Source: Hanol Publishing)

The underfill material is a vital component to guarantee the reliability of joints in processes like flip chip and chip stacking using through-silicon via (TSV). Accordingly, the material needs to meet specific requirements for cavity filling, interfacial adhesion, coefficient of thermal expansion¹¹, thermal conductivity, and thermal resistance.

¹¹Coefficient of thermal expansion (CTE): A material property that indicates the extent to which a material expands upon heating.

Wafer Support System: Using a Carrier, TBA, & Mounting Tape to Assemble the Package

The wafer support system (WSS) process requires a carrier that can support a thin wafer and a temporary bonding adhesive (TBA). After debonding the carrier, mounting tape is also required to firmly attach the thin wafer that formed bumps on its front and back to a ring frame.

Among all the materials that are involved in a WSS, the TBA is the most important. When the wafer and carrier are bonded together to form a TSV package, the TBA must maintain strong adhesion during the backside process without damaging the bumps on the wafer. Thus, there must be no outgassing¹², voids¹³, delamination¹⁴, and bleeding out—the seeping out of adhesive from the sides of the wafer during bonding. Consequently, it is crucial to have both thermal stability and chemical resistance, while the carrier must also be easy to remove without leaving any residue.

¹²Outgassing: The release of a gas from a liquid or solid material. This gas can cause defects in semiconductor devices if it condenses on a surface and affects the device’s properties.
¹³Voids: A gap in a material caused by the formation of air bubbles. These voids can expand during high-temperature processes or debonding, increasing the risk of damage or device failure.
¹⁴Delamination: The separation of two previously connected surfaces in a semiconductor package.

Even though silicon carriers are preferred, glass carriers are also frequently used. This is especially true for processes that use light such as lasers during debonding as they require the use of glass carriers.

The Building Blocks of Semiconductor Packaging

Throughout these articles on the materials that make up conventional packaging and WLP, it has become clear that the type and quality of materials have had to evolve to keep pace with the development of semiconductors. The various reliability tests for semiconductor packages will be introduced in the next episode, which will conclude the back-end process series.

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The post Semiconductor Back-End Process Episode 10: Exploring the Roles of Materials in Wafer-Level Semiconductor Packaging first appeared on SK hynix Newsroom.

Fan-in Wafer-Level Chip-Scale Package (WLCSP) Process

In a fan-in WLCSP, a tested wafer enters the packaging line and a layer of metal film is created using sputtering. A thick layer of photoresist is then applied to the metal film as the photoresist must be thicker than the metal wiring used for packages. Photolithography is used to form patterns on the photoresist, and these exposed areas are copper electroplated to form the metal wiring. Next, the photoresist is stripped, and the excess thin metal film is removed using chemical etching. A dielectric layer is then formed on top, and photolithography is used to remove only the areas where the solder balls will be placed. Thus, this layer is also referred to as “solder resist.” It serves as the WLCSP’s passivation layer, or final protective layer, and distinguishes the area where the solder ball will be placed. Without this layer, solder balls would continue to melt on top of the metal layer and would not retain their globular shape when they are attached using methods such as reflow soldering.

Solder balls are attached to the dielectric layer through solder ball mounting after the layer forms a pattern through photolithography. Once the solder balls are mounted, the packaging process is complete and individual fan-in WLCSPs can then be created by dicing the wafer.

Solder Ball Mounting Process

▲ Figure 1. A bird’s eye view of wafer-level reflow equipment (Source: Hanol Publishing)

The process of solder ball mounting involves attaching solder balls onto a WLCSP for packaging. The key distinction from placing solder balls on a substrate in conventional packaging lies in the fact that solder balls are placed atop a wafer. Thus, flux application, solder ball mounting, and the reflow process follow the same steps, except that the stencil utilized to applying flux and mounting solder balls has the same size as the wafer itself.

Additionally, the reflow equipment takes a hot plate-based approach, as depicted in Figure 1, as opposed to the convection reflow method involving conveyers. In wafer-level reflow equipment, different temperatures are applied to wafers as they progress through the various stages. This ensures that packaging can progress while maintaining a temperature profile for the reflow process.

Flip Chip Bump Process

The process of forming bumps in a flip chip package is carried out in the wafer-level process, while the subsequent steps are conducted in the conventional packaging processes.

▲ Figure 2. An overview of the flip chip packaging process

▲ Figure 3. The steps for forming a flip chip bump

As the bumps must be sufficiently high, it is necessary to select a photoresist that can be thickly applied to the wafer-level package. Copper pillar bumps (CPB)¹ are formed through copper plating followed by solder plating. This solder is typically a lead-free tin/silver alloy. Once plating is complete, the photoresist is removed and the under bump metallurgy (UBM)² film formed by sputtering is removed via metal etching. The bumps are then molded into a spherical shape using wafer-level reflow equipment. The solder bump reflow process here serves to minimize height discrepancies among the bumps, reduce the surface roughness of the solder bumps, and eliminate oxides from the solder, all of which enhance the bonds during the flip chip bonding process.

¹Copper pillar bump (CPB): The structure of the bump for flip chip bonding to reduce the gap between the bumps. Copper is used to form the pillars that have bumps on top of them.
²Under bump metallurgy (UBM): The metal layer formed under flip chip bumps.

Redistribution Layer (RDL) Process

▲ Figure 4. An overview of the packaging process using a redistribution layer (RDL)

▲ Figure 5. The steps for forming a redistribution layer (RDL)

Used for chip stacking, the redistribution layer (RDL) process creates a new pad by forming an extra layer of metal wiring over a pad formed on a wafer. Consequently, the packaging processes after the RDL process follow conventional packaging processes, as depicted in Figure 4. During chip stacking, the die attach and wire bonding steps are repeated equally for each chip that needs to be stacked.

In the RDL process, sputtering is first used to create a thin layer of metal film, which is covered with a thick layer of photoresist. A pattern is created through photolithography so that the exposed areas of the pattern can be electroplated with gold to form metal wiring. Since redistribution itself is a process of rebuilding the pad, the ability to form strong bonds is essential for wire bonding. This is why gold, which is widely applied for wire bonding, is used for plating.

Fan-out Wafer-Level Chip-Scale Package (WLCSP) Process

The process of fabricating a fan-out WLCSP begins by applying tape to a wafer-shaped carrier. After wafer dicing, the high-quality chips are attached on top of the tape at regular intervals. The spaces between the chips are filled with wafer molding, resulting in a new shape. Once the wafer molding is complete, the carrier and tape are removed. Next, metal wiring is created on the newly formed wafer using wafer equipment, followed by the attachment of solder balls for packaging. Finally, the wafers are diced into individual packages.

Wafer Molding

To create a fan-out WLCSP, wafer molding is an essential step. The wafer molding process entails placing a wafer—in the case of a fan-out WLCSP, a wafer-shaped carrier with chips attached to it—into a molding frame. An epoxy molding compound (EMC)³, which can be in the form of a liquid, powder, or granules, is then added to the frame and compression and heat are applied to mold the setup. Wafer molding is not only an essential process for fan-out WLCSPs, but it is also a requirement for a known good stacked die (KGSD)⁴ that uses TSV, which will be discussed later.

³Epoxy molding compound (EMC): A heat dissipation material based on an epoxy resin, or a type of thermosetting polymer. It seals semiconductor chips to protect them from external environmental factors such as heat, moisture, and shock.
⁴Known good stacked die (KGSD): A product comprised of stacked chips that have been tested and confirmed to be of good quality. A prime example is HBM.

Through-Silicon Via (TSV) Package Process

Figure 6 illustrates the process steps of fabricating a TSV package using a via-middle⁵ approach. First, vias are formed during wafer fabrication. Subsequently, solder bumps are formed on the wafer’s front side during the packaging process. The wafer is then attached to a carrier wafer and backgrinded. After bumps are formed on the backside of the wafer, the wafer is diced into units of chips and stacked.

⁵Via middle: A type of TSV that fabricates TSVs after the formation of CMOS but before the metal layers are formed.

To provide a brief overview of the process of forming TSVs with middle vias, transistors such as CMOS are initially fabricated on a wafer during the front-end of line (FEOL) process. Then, using a hard mask (HM)⁶, a pattern is created where the TSV will be formed. Next, the areas without the hard mask are removed through dry etching to create deep trenches. Insulating films, such as oxides, are subsequently deposited via chemical vapor deposition (CVD). This insulating film serves to isolate metals like copper that will later fill the trenches, preventing the metals from contaminating the silicon. Additionally, a thin layer of metal that acts as a barrier is created atop the insulating film.

⁶Hard mask (HM): A mask that creates finer patterns as it is made up of harder materials than soft masks. Since an HM is not photosensitive in itself, additional patterning needs to be formed with the application of photoresist, followed by the subsequent etching process.

This thin layer of metal is used to electroplate copper. After electroplating, the wafer’s surface is smoothed through chemical mechanical polishing (CMP), which simultaneously eliminates all of the copper from the surface of the wafer, ensuring that copper remains solely within the trenches. This is followed by the back-end of line (BEOL) process to complete the wafer fabrication.

▲ Figure 6. The steps of the TSV packaging process (Source: Hanol Publishing)

There are two main types of packages that can be created when producing chip stack packages using TSV technology. The first is a package that uses a substrate with 3D chip stacking technology. The second type involves creating a KGSD and then using it to make a 2.5D or 3D package. The following section will explain the processes of fabricating KGSDs and using them to create 2.5D packages.

As a chip stack package which uses TSV, KGSD has to undergo additional packaging processes such as 2.5D packaging, 3D packaging, and fan-out WLSCP. A prime example of a KGSD product is high bandwidth memory (HBM). Since a KGSD needs to go through additional packaging processes, the connection pins are formed as fine solder bumps rather than conventional solder balls. As a result, while chips in a 3DS package are stacked on a substrate, chips in a KGSD are stacked on a wafer, which also serves as the bottommost chip of the KGSD. In the case of HBM, the chip at the bottom is referred to as the base chip or base wafer, while the chips stacked above it are known as the core chips.

To explain the process steps, bumps are formed on the front surface of both the base and core wafers through a flip chip process. In the context of a 2.5D package, the base wafer necessitates the arrangement of bumps so that they can be attached to interposers. Conversely, the core wafer forms a bump layout that facilitates chip stacking on the front of the wafer. After bumps are formed on the frontside of the wafer, the wafer should be thinned, and bumps should also be formed on the wafer’s backside. However, as previously mentioned during the introduction of the backgrinding process, it is important to note that thinning the wafer can induce the wafer to warp. While conventional packaging makes it possible to have wafers taped to ring frames following the backgrinding to prevent wafer warpage, this method is not viable in TSV packaging where bump formation occurs on the wafer’s backside. This is exactly why the wafer support system (WSS) was developed. Under the WSS, the frontside of the wafer with bumps is bonded to a carrier wafer with a temporary adhesive. At the same time, the backside of the wafer is grinded to thin it. Since it is attached to the carrier wafer, the thinned wafer does not warp.

Additionally, since the carrier wafer is also in the form of a wafer, it can be processed using wafer equipment. Using this structure, bumps are created on the core wafer’s backside. Once bumps are formed on both sides of the core wafer, the carrier is debonded. Then, the wafer is taped to a ring frame and diced in the same manner as conventional packaging processes. The base wafer remains attached to the carrier wafer as it removes chips that are diced from the core wafer to stack on top of the base wafer. When chip stacking is complete, the base wafer is molded while the carrier wafer is debonded. In this way, the base wafer becomes a molded wafer with core chips stacked on it. This wafer is grinded to the target thickness suitable for making a 2.5D package and then diced into chips to form KGSDs. This finished HBM is packed and shipped to customers who will make 2.5D packages.

Wafer Support System (WSS) Process

A WSS refers to a system that allows further processing on the backgrinded surface of a thinned wafer. This process occurs prior to the completed backgrinding process. The WSS process involves two main steps: carrier bonding, which involves attaching a carrier to a wafer for TSV packaging; and carrier debonding, where the carrier is detached after completing processes like forming bumps on the wafer’s backside.

Figure 7 depicts the WSS process steps, where carrier bonding involves applying a temporary adhesive to the wafer before attaching it to the carrier. Carrier debonding involves removing the carrier after processes on the backside are completed and ensuring the wafer is cleaned to remove any residual adhesive.

▲ Figure 7. The steps of the wafer support system (WSS)

There are several considerations to be taken into account in carrier bonding: the overall thickness of the wafers bonded through carrier bonding should be uniform; there should be no voids at the bonded joints; the alignment of the two wafers should be accurate; there should be no adhesive-related contamination at the edge of the wafers; and wafer warpage should be minimized during the process. During the carrier debonding, there should also be: no damage such as chipping⁷ or cracking to the wafer that is separated from the carrier; no adhesive residue; and no deformation of the bumps.

⁷Chipping: The breaking of the edges or corners of a chip or wafer.

Debonding stands out as a relatively complex and critical step within the WSS process. As a result, various debonding methods have been proposed and developed, accompanied by the development of different temporary adhesives for each method. Typical methods include thermal techniques, laser ablation followed by peel-off, chemical dissolution, and chemical cleaning after mechanical lift-off.

Wafer Edge Trimming Process

▲ Figure 8. A comparison of the edges of untrimmed (upper image) and trimmed (lower image) wafers

After a wafer for a TSV package is bonded to a carrier wafer and then backgrinded, it will have sharp edges, as shown in the red circle in the upper image of Figure 8. In this state, the wafer undergoes subsequent processes such as photolithography, metal film formation, and electroplating to form bumps on the backside. However, these processes elevate the risk of chipping the wafer’s edge. Cracks at the edge could propagate inward, eventually rendering further processing impossible, thereby resulting in significant yield loss. To preemptively overcome this problem, the edge of the frontside of the wafer designated for TSV packaging is trimmed and removed before it is bonded with the carrier wafer. When the trimmed wafer is bonded to the carrier wafer and backgrinded, the sharp edge’s prominence diminishes, as shown in the lower part of Figure 8. Consequently, the risk of chipping during subsequent processes is eliminated. The trimming process employs a rotating wafer dicing blade that traverses the wafer’s edge, removing a designated segment of the edge.

Stacking Process

In TSV packaging, the bumps formed on the front and back of wafers are bonded together for stacking. Like in flip chip bonding, mass reflow (MR) and thermocompression are used for bonding. Depending on the type of stacking, the processes are classified as chip-to-chip stacking, chip-to-wafer stacking, and wafer-to-wafer stacking.

When stacking chips with TSVs, micro bumps are used. Therefore, the gaps between these bumps are small, as is the spacing between stacked chips. This is why thermocompression, known for its high reliability, has been widely adopted. However, thermocompression has the disadvantages of taking a long time and has low productivity as heat and pressure must be applied for a certain period during bonding. As such, there’s a growing trend toward adopting MR as an alternative bonding technique.

Looking Beyond the Types of Wafer Packaging

After discussing the two main groups of conventional and wafer-level packages in these two last episodes, the next chapter in our series will delve into the materials that make up the various components of these packages. In particular, it will cover the unique properties of these small materials and analyze how they affect the performances of these semiconductor products.

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Packaging With a Fully Intact Wafer

WLP refers to the process that is performed before the wafer is diced. It generally includes fan-in wafer-level chip scale packaging (WLCSP) and fan-out WLCSP in which the entire process is performed while the wafer is still fully intact. Nevertheless, redistribution layer (RDL) packaging, flip chip packaging, and through-silicon via¹(TSV) packaging are also generally categorized as WLP even if only a part of their processes are performed before the wafer is diced. Depending on which of these types of packages is used, there are variations in the type of metal and pattern formed by electroplating². However, they all follow a similar sequence during packaging as described below.

¹ Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.

² Electroplating: A reaction where oxidation occurs at the positive plate to produce electrons which are transmitted to a wafer with a solution that has metal ions that are negative plates to become metal.

After wafer testing is performed, a dielectric layer is created on the wafers as needed. The dielectric layer then exposes the chip pad again, following the first exposure during testing, with photolithography.

Afterwards, a metal layer is applied on the surface of the wafer through sputtering³. This metal layer enhances the adhesion of the electroplated metal layer that will be formed and acts as a diffusion barrier to prevent the development of chemicals within metals. It also functions as a pathway for electrons during the electroplating process, and applies photoresist to create an electroplating layer while a pattern is created through photolithography. A thick metal layer is then formed by electroplating. When electroplating is completed, the next step is to proceed with the PR stripping process while the remaining thin metal layers are removed by etching. As a result, the electroplated metal layers are formed on top of the wafers in the desired patterns. This pattern serves as the wiring for fan-in WLCSP, the pad redistribution in RDL packaging, and the bumps in flip chip packaging. The following sections will take a closer look at each of these processes.

³ Sputtering: A process in which plasma ions physically collide with a target and removes the target’s material so it can be deposited onto the wafer.

▲ Figure 1. The steps involved in various wafer-level packaging processes

Photolithography: Sketching Patterns on a Masked Wafer

Photolithography, a combination of “-litho” (stone) and “graphy (drawing),” refers to a printing technique. In other words, photolithography is a patterning process in which a photosensitive polymer called a photoresist is applied to the wafer and selectively exposed to light through a mask that has a desired pattern on it. The areas that are exposed to light are developed, and the required pattern or shape is created. The sequence of this process is shown in Figure 2.

▲ Figure 2. The steps of photolithography

In WLP, photolithography is primarily used to form patterns on dielectric layers, to create an electroplated layer by photoresist patterning, and to create metal wiring by etching diffusion layers.

▲ Figure 3. A comparison of photography and photolithography

To understand photolithography more clearly, it will be helpful to compare it with photography. As shown in Figure 3, photography uses sunlight as its light source to capture a photo of its subject, which could be an object, landscape, or a person. On the other hand, photolithography requires a specific light source to transfer patterns on a mask to an exposure tool. Lastly, the role of the film in a camera is equivalent to the photoresist that is applied to a wafer during photolithography. Consequently, there are three methods to apply a photoresist on the wafer as shown in Figure 4. They consist of spin coating, film lamination, and spray coating. After applying the photoresist, soft baking is performed to remove solvents to ensure that the viscous photoresist remains on the wafer and maintains its thickness.

As shown in Figure 5, spin coating places viscous photoresist onto the center of a spinning wafer so the photoresist is spread towards the edges due to centrifugal force. This makes the photoresist form a uniform thickness on the wafer. If the viscosity of the photoresist is high while the spin speed is low, the photoresist will be applied thickly. Conversely, if the viscosity is low and the spin speed is high, it is applied thinly. In the case of wafer-level packages, especially flip chip packages, they require a photoresist layer with a thickness ranging from 30 to 100 micrometers (μm) to form solder bumps. However, it is not easy to achieve the desired thickness in a single spin coating. In some instances, it is necessary to repeat the application of photoresist and soft baking more than once. Accordingly, when a thick photoresist is required, it is effective to use lamination as it makes the film the desired photoresist thickness from the start. It is also more cost-effective because there is no waste from the wafer during processing. However, if there are rough surfaces on the wafer’s structure, it can be difficult to adhere the film to the wafer which can lead to defects. For wafers that have very rough surfaces, a uniform thickness of photoresist can be achieved through spray coating.

▲ Figure 4. The three methods to apply photoresist

▲ Figure 5. An overview of spin coating

After the photoresist is coated and soft baked, the next step is to expose it to light. By shining light through a pattern formed on the mask, the photoresist on the wafer receives the image of the pattern. When using a positive photoresist that weakens when exposed to light, the mask needs to have holes in areas that are going to be removed. However, when using a negative photoresist that hardens when exposed to light, the mask must have holes in the areas that need to remain. For WLP, a mask aligner⁴ or a stepper⁵ is typically used as the process equipment for photolithography.

⁴ Mask aligner: One of the exposure tools that aligns the pattern on the mask and the wafer so that light can pass through them simultaneously.

⁵ Stepper: A machine where the stage moves in steps and photolithography is performed by a shutter that opens and closes to allow light to pass through.

Development is the process of dissolving the parts of the photoresist that have been weakened through photolithography with a developer solution. As shown in Figure 6, there are three types of development: puddle development that pours the developer onto the center of the wafer so it spins at a low speed, tank development that immerses multiple wafers in the developer at the same time, and spray development that sprays the developer onto the wafer. Figure 7 shows an overview of a chamber for puddle development. After the puddle development is finished, the photoresist takes on the desired pattern through photolithography.

▲ Figure 6. Three different methods of development

▲ Figure 7. An overview of a chamber for puddle development

Sputtering: Forming Thin Films on the Wafer

The process of sputtering is a type of physical vapor deposition⁶ (PVD) that forms a thin film of metal on a wafer. If the metal film formed on the wafer is below the bumps as seen in flip chip packages, it is called an under bump metallurgy (UBM). Typically, it is in the form of two or three layers of metal film, including an adhesion layer, a current carrying layer that provides electrons during electroplating, and a diffusion barrier with solder wettability⁷ that suppresses the formation of compounds between the plating layer and the metal. If the layers are comprised of titanium, copper, and nickel, the titanium acts as the adhesion layer, the copper acts as the current carrying layer, and the nickel acts as the diffusion barrier. Accordingly, the UBM has a significant impact on the quality and reliability of flip chip packages. As for metal layers like an RDL and a WLCSP that are used to form metal wiring, they usually consist of an adhesion layer and a current carrying layer that improves adhesion.

As Figure 8 shows the sputtering process, it starts with argon gas transforming into plasma⁸ and colliding with a target that has the same composition as the metal on which positive argon ions will be deposited. The impact of the collision removes the metal particles from the target so they are deposited on the wafer. The metal particles deposited by sputtering have a consistent directionality. Even though a flat plate is deposited with a uniform thickness, plates in the shape of a trench or vertical interconnect access (via) can have different results. Such irregular shapes can make the deposition thickness of the wall’s surface that is parallel to the metal deposition become thinner than the plate’s floor that is perpendicular to the metal deposition.

⁶ Physical vapor deposition (PVD):  A process used to produce a metal vapor that can be deposited on electrically conductive materials as a thin and adhesive pure metal or alloy coating.

⁷ Wettability: The phenomenon where a liquid spreads on the surface of a solid due to the interaction between the liquid and the solid surface.

⁸ Plasma: A state of matter that is electrically neutral due to the coexistence of freely moving protons and electrons. When heat is continuously applied to a gaseous substance to raise its temperature, a collection of particles consisting of ions and free electrons is created. It is also called the “fourth state of matter” in addition to solid, liquid, and gas.

▲ Figure 8. The fundamentals of sputtering

Electroplating: Forming Metal Layers to Bond

Electroplating is the process of depositing metal ions of an electrolyte solution as metal on a wafer. This is possible through a reduction reaction using externally supplied electrons. In WLP, electroplating is used to form thick metal layers such as metal wiring for electrical connections or bumps for junctures. Just as Figure 9 illustrates, a metal undergoes oxidation at the anode to become an ion and releases electrons to the external circuit. The metal ions oxidized at the anode or present in the solution receive electrons and undergo a reduction reaction to become metal. In the electroplating process for WLP, the cathode plate becomes the wafer. The anode plate is made of the metal to be plated, but it also uses an insoluble electrode⁹ such as platinum. If the anode plate is made of the metal to be plated, metal ions are dissolved from the anode plate and continuously distributed to maintain a consistent ion concentration in the solution. However, if an insoluble electrode is used, metal ions expended while being plated on the wafer must be periodically replenished in the solution to maintain the ion concentration. Figure 10 below shows the electrochemical reactions that occur at the cathode and anode, respectively.

⁹ Insoluble electrode: An electrode used primarily in electrolysis and plating. It is neither chemically nor electrochemically soluble. Materials such as platinum are used for its creation.

▲ Figure 9. The process of electroplating

▲ Figure 10. Electrochemical reactions at the cathode and anode expressed as formulae

The equipment that electroplates a wafer is typically placed so the side of the wafer to be plated faces down while the anode is positioned below the solution. Electroplating happens when the solution flows toward the wafer and forcefully collides with the surface. At this point, patterns formed from photoresist can come into contact with the solution on the parts of the wafer to be plated. Electrons are distributed through the electroplating equipment at the edge of the wafer and eventually meet the metal ions in the solution at the patterned parts. They then combine with metal ions inside the solution where the patterns are formed to go through a reduction reaction and grow to form metal wiring or bumps.

PR Stripping and Metal Etching: Removing the Photoresist

Once the processes that use the photoresist pattern are complete, the photoresist must be removed via PR stripping. PR stripping is a wet process that uses a chemical solution called a stripper, and implements development methods such as puddle, tank, or spray. After a process like electroplating forms metal wiring or bumps, the metal film formed by sputtering must also be removed. This is necessary as the entire wafer will be electrically connected and result in a short circuit if the metal film is not taken off. The metal film is removed by wet etching with an acid-based etchant that can dissolve the metal. While the technique is similar to PR stripping, puddle development has been used more widely as metal patterns on the wafer have become finer.

A More Efficient and Reliable Packaging Process

WLP strives for efficiency, miniaturization, and reliability through the above mentioned stages that begin with sketching patterns through photolithography and culminate in removing the applied photoresist through PR stripping. The next episode will look into the different types of WLP that use technologies such as fan-in and fan-out WLCSP, RDL, flip chip, and TSV.

Read articles from the Front-End Process series

Read articles from the Back-End Process series

The post Semiconductor Back-End Process Episode 7: The Wafer-Level Packaging Process first appeared on SK hynix Newsroom.