This episode will explain the various packaging and testing practices that are required in the later stages of semiconductor manufacturing to ensure the accuracy and quality of the products.

The Back-end Process of Semiconductors

The simple order of the manufacturing process consists of the wafer process, the packaging process, and testing. The front-end process refers to the manufacturing of wafers, while the back-end process consists of packaging and testing. Even the wafer manufacturing process is split into a front-end and back-end process. The front-end typically consists of the CMOS-making process, and the back-end refers to the metal wiring formation process that comes after CMOS is made.

▲ Figure 1. The relationship between the semiconductor manufacturing process and the semiconductor industry (Source: Hanol Publishing)

Figure 1 is a flow chart that shows the relationship between the semiconductor manufacturing process and the semiconductor industry. Companies like Qualcomm and Apple that only design semiconductors are called “fabless.” Products designed by fabless companies are made into wafers, and the facilities that produce these wafers are called “foundries.” Global companies with these facilities include Taiwan’s TSMC and UMC. Then, there are companies that test and package products that were designed by fabless vendors and, later, made into wafers at foundries. These are called OSAT (Outsourced Assembly and Test) which include companies such as ASE and Amkor. Finally, there are the companies that do everything from design, wafer production, and packaging, to testing. These companies are called IDMs (Integrated Device Manufacturer), and SK hynix is one of the leading IDMs in the world.

As shown in Figure 1, the first phase of the packaging and testing process is wafer testing. Afterwards, packages are made in the packaging process and followed by the package test stage.

One of the main reasons for semiconductor testing is to prevent the shipment of defective products. Therefore, it’s necessary to have an exhaustive inspection process that includes various types of testing to secure the quality and reliability of the products. But these extensive processes increase testing time, equipment, required manpower, and manufacturing costs.

Testing Temperature, Speed, and Movement

▲ Table 1. Test classification (Source: Hanol Publishing)

Tests can be divided into wafer tests and package tests depending on the form of the subject being tested, but the types of testing can be divided into temperature, speed and operation—as shown in Table 1.

The temperature applied to the test subject is the standard for temperature tests. Hot tests apply a temperature of 10% or more above the maximum temperature stated in the products’ spec¹, while cold tests apply a temperature 10% or less than the minimum temperature. Room tests usually apply a temperature of 25°C (77°F). Since semiconductor products are used in different settings with various temperatures, these tests exist to verify the product’s ability to operate under various temperatures and to know their temperature margins.

¹Spec: As the abbreviation for “specifications,” the term refers to the blueprint that outlines what’s required during the manufacturing of products such as design regulations, manufacturing methods, or regulations of desired properties in products.

Speed tests are divided into core tests and speed tests. Core tests evaluate whether the core operation, or the main purpose, of a semiconductor performs properly. In the case of semiconductor memories that store data, testing looks at whether data is properly stored in the cell area. Speed tests measure the operating speed, so products are evaluated on whether they can operate at the desired speed.

Operation tests can be divided into three categories: DC tests, AC tests, and function tests. DC tests allow currents to pass into DC so electrical measurements are shown in the form of currents or voltage. Function tests turn on each function of a product to check if they operate properly.

The Process of the Wafer Test

Wafer tests inspect the properties and qualities of the numerous chips that are on a wafer. For the test, the testing equipment and the chips need to be connected to send currents and signals to the chips.

Since packaged products have pins like solder balls to connect to the system, electrical connection with the test equipment is relatively easy. However, in the case of wafers, a probe card is required.

▲ Figure 2. Infographic of wafer testing system (Source: Hanol Publishing)

As shown in Figure 2, many probes² are built on the top of the card to make physical contact with the pad of the wafer. The wiring that connects the probe and the test equipment is built into the card. These probe cards are mounted on the tester head so they can make contact with the wafer on the prober where they are loaded.

²Probe: A needle that makes physical and electrical contact with the wafer pad on the probe card.

When a wafer is loaded with the front side facing up, the probe card on the right is turned over. Then, a probe is mounted on a tester head so that the wafer and probe card can come into contact. At the same time, the temperature control device can apply a temperature in accordance with the test temperature condition. The test system applies the current and signal through the probe card and then reads the test results from it.

Wafer testing usually follows the following process: EPM (Electrical Parameter Monitoring) → Wafer Burn-in → Test → Repair → Test. These steps are described below.

EPM (Electrical Parameter Monitoring)

The purpose of testing is to filter out defective products, but it also has the goal of improving products that are under development or being mass-produced by providing feedback on their deficiencies. The main purpose of EPM is to give feedback on the wafer manufacturing process by evaluating and analyzing the electrical characteristics of the product’s unit devices. This is a process of measuring transistor characteristics and contact resistance using electrical methods before actual testing to verify whether the manufactured wafer satisfies the basic properties suggested by the design and device departments.

Wafer Burn-in

▲ Figure 3. Defect rate according to product usage time (Source: Hanol Publishing)

Figure 3 shows the defect rate during product life as a function of time. As it resembles the shape of a bathtub, it’s also called a bathtub graph. In the early stages of its lifecycle, there are many early failures, or failures caused by manufacturing defects. When defects from manufacturing are resolved, random failures, or the defect rate during the service life of the product, happen less often. Moreover, when the product wears out, defect rates rise again.

Burn-in is carried out to detect early defects in advance by prompting potential product defects on purpose. Wafer burn-in applies temperature and voltage to stress the wafer product, so any defects that may appear in the initial failure period are exposed.

Wafer Test

Wafers that went through early failure tests via wafer burn-in are then tested with a probe card for a wafer test. Wafer testing is the process of examining the electrical characteristics of a chip at the wafer level. The test serves several purposes including pre-detection of defective chips, giving device and design feedback through wafer-level verification, and sorting out defects that will occur during packaging/mounting³ ahead of time. This last procedure ensures that the cause of defects at the wafer level can be analyzed and feedback on the manufacturing process can be provided. If defects are sorted in the wafer test, some of the defective cells⁴ can be replaced with redundancy cells through a process called repair.

³Mounting: The process of assembling a board or system by mechanically and electrically attaching components.

⁴Cell: Refers to the minimum set of elements required to store data in a memory element. A cell in DRAM consists of one transistor and one capacitor.

Repair

Mainly performed with semiconductor memories, the process of repair replaces defective cells with surplus cells by applying the repair algorithm. For example, if 1 bit is defective as a result of a wafer test consisting of a DRAM 256-bit memory, the product will have 255 functioning bits. However, if a surplus cell replaces the defective cell, the chip becomes a quality product that satisfies the 256-bit spec again and can be sold to customers. Through repair, yields eventually increase. For this reason, semiconductor memories create surplus cells during design so they can make substitutes according to test results.

Packaging Test

A chip determined to be a quality product in the wafer test undergoes a packaging process, and the completed package undergoes a packaging test again. Even if the wafer is found to be a quality product during the wafer test, defects may occur during the packaging process. Therefore, the packaging test is essential.

For the packaging test, the package pin (the solder ball in #3 of Figure 4) should be faced down and put into the socket so that it can come into contact with the pins in the socket. Then, the packaging test socket is mounted on a package test board to perform a packaging test.

▲ Figure 4. Packaging test system (Source: Hanol Publishing)

TDBI (Test During Burn-in)

Burn-in is a test that stresses a product with voltage and temperature in order to eliminate potential defects in the product at an early stage. Burn-in performed after packaging is called TDBI. Burn-in can be performed on the wafer or on the package, but most semiconductor manufacturers burn-in the wafer and the package simultaneously.

Test

This is the process of determining whether a semiconductor operates normally in the user’s environment as defined in the datasheet⁵. A temperature corner test is performed to verify that the product meets the specifications for AC/DC factor weakness and operations requested by the customer in the Cell & Peripherals areas.

⁵Datasheet: A regulation document that defines the properties that can be found in a semiconductor product.

Visual Test

When testing is completed, the test results must be recorded on the exterior of the package and, consequently, laser marking is required. After the package test has been completed and marked, the quality package is placed in the package tray. Now, the only remaining step is to ship the product to the customer. Therefore, it is necessary to conduct a final visual inspection before shipping to the customer to sort out defects in the exterior. During the visual test, manufacturers look for cracks, markings, improper tray placements, and other defects. For solder balls, manufacturers sort out pressed balls, missing balls, and other defects.

Read articles from the Front-End Process series

Read articles from the Back-End Process series

The post Semiconductor Back-End Process Episode 1: Understanding Semiconductor Testing first appeared on SK hynix Newsroom.

1. Development of Wafer Dicing

Figure 1. Change of the dicing method for separating into individual chips (singulation)

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The front-end process and back-end process develop by influencing each other in various ways. The development of the back-end process is a factor that determines the structure or location of a die (a chip separated in a hexahedral form) on a wafer, or the structure or location of a pad (electrical connection path) on a die in the front-end process. Conversely, the development of the front-end process changes the procedure and method of back grinding or die sawing the wafer in the back-end process. As a result, the appearance of the package which becomes smaller has a great influence on the back-end process. Depending on the changes in the appearance of the package, the number of times for dicing and the procedure and the type of dicing are determined accordingly. ▶ Refer to “Light, Thin, Short and Small”, The Development of Semiconductor Packages Now we will have a look at the five-step dicing method according to the development of chip singulation.

2. Scribe Dicing

Figure 2. Scribe dicing method in the early period: Physical separation (breaking)
after scribing @ wafers with a diameter of 6 inches or less

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In the early days, only “breaking”, a method of applying an external force, was performed as a method of separating a die, which is a hexahedral semiconductor chip, with a transistor scribed from a wafer; however, this method caused damages such as chipping (chipped edges) or cracks to a die separated from a wafer. In addition, another problem was that burrs (stumps generated after cutting) of the metal layer were not sufficiently removed, making the cut surface rough.

To prevent these problems, a scribing method where the wafer surface is bladed to a depth of about half before breaking is applied. Scribing means making a groove in advance by sawing (half cutting) the front of a wafer by using a blade wheel. This method of scribing between dies and breaking them into individual chips was mainly used in wafers under 6 inches in the early days.

3. Blade Dicing (or Blade Sawing)

Figure 3-1. Blade dicing (or blade sawing) method @ General conventional method

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Scribe dicing has since evolved into a blade dicing (or sawing) method which uses a blade two or three times in a row. This method remedies the disadvantage of chipping, which the edges are broken due to external damage, when breaking after scribing and protects the die during singulation. This can also be referred to as step dicing. Instead of breaking after the first breaking, it performs blading again as the second step.

Figure 3-2. Attachment and detachment of film during blade dicing (sawing)

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To protect a wafer or a die from external damage during blading, an adhesive tape is attached to the wafer in advance, for safer singulation. Contrary to back grinding where the tape is attached to the front side of the wafer, dicing tape is attached to the back side of the wafer. ▶ Refer to < Back Grinding Determines the Thickness of a Wafer Back> This tape on the back side removes the tape by itself during the process of die bonding, where the separated chip is mounted to the PCB or lead frame. As the friction is high during blading, deionized (DI) water should be continuously sprayed from all directions. In addition, diamond grains are firmly attached to the blade wheel so that it can dig solid silicon better. At this time, the kerf (blade thickness), which is the width of the groove created, must be even, without going beyond the width of the scribe line.

The advantage of blade sawing is that it can cut a large number of wafers in a short time with the conventional method which has been used the most and for the longest until recently; however, if the feeding speed for digging the wafer is increased too much, the possibility of chipping is higher. For this reason, the number of rotations of the blade wheel should be adjusted to around 30,000 times per minute. As this suggests, semiconductor process technology is often established through accumulating know-how obtained through trials and errors for a long time (The next session about die bonding will cover the die attach film (DAF) associated with dicing).

4. Dicing Before Grinding (DBG): Dicing Order Change Method

Figure 4. Existing blading dicing method and dicing before grinding (DBG) method

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As the diameter of wafers increased to 12 inches and the thickness became very small, chipping or cracking, which did not cause a big problem even after blade dicing on 8-inch wafers, started to become an issue. In response to this, to drastically reduce the physical damage applied to wafers, a process of dicing before grinding (DBG) was introduced to replace the standard process of conventional dicing. In this method, blading, which was performed in blade dicing, is not performed for two or three consecutive times. Instead, after the primary blading, grinding is performed continuously until the chips are separated while adjusting the thickness of a wafer by back grinding. This method is a more advanced one than the previous blading dicing method. As it has the effect of reducing the damage during the second blading, this method is common in wafer-level packaging.

5. Laser Dicing

FFigure 5. Comparison of conventional laser dicing (grooving) method and laser stealth dicing (SD) method

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For dicing which is applied to processes including wafer level chip scale package (WLCSP) process, there exists a method using a laser. When using this method, the chip quality is excellent with the small amount of chipping and cracking; however, as the productivity is relatively low when the wafer thickness is 100 μm or more, this method is more widely used for thinner wafers. Laser dicing is performed by digging out silicon by applying a laser with high energy to the scribe line of the wafer. In the conventional laser method where the damage created by heat or physical contact with a laser is applied to the wafer surface, grooves are generated and the cut silicon debris adheres to the front surface. For this reason, the wafer surface should be coated in advance to prevent this. The conventional laser method is conceptually similar to blade dicing in the sense of directly cutting the wafer surface.

Laser stealth dicing (SD) is a method which cuts the inner part of a wafer with laser energy first and then applies external pressure to the tape attached to the outside to break the skin and separate the chips. When pressure is applied to the tape attached to the back side, the wafer is instantly bent upwards by the extended tape and the chips are singulated individually. When using this method, there is no debris generated when dicing the surface directly with a laser, and the kerf, the width of the cut line, is also narrowed, so that many chips can be placed on the wafer. In addition, the number of chipping and cracking, which determines the overall dicing quality, is also small. For these reasons, this method is expected to become a popular technology in the near future.

6. Plasma Dicing

Plasma dicing is a dicing method that has been evolving recently. It uses plasma etching in the fabrication (fab) process. This method has less environmental impacts as it uses a semi-gastric material rather than a liquid. Also, as it is applied to the entire wafer all at once, the speed of singulation per chip is relatively fast. In this method, it can be cumbersome in the procedure as a chemical reaction gas is used as raw material and a complicated etching process is required; however, unlike blade dicing or laser dicing which accompanies great and small external damage, there is no external damage in this method, which acts as a great advantage. This reduces the defect rate as well, leading to an increase in the number of chips.

In recent times, the thickness of wafers has been decreasing to 30 μm and copper (Cu) or materials with a small relative dielectric constant (low-k materials) are being used. Accordingly, the plasma dicing method is expected to be more preferred to prevent the occurrence of burrs after processing. Since the technology for plasma dicing is also developing further, it is evolving in a way that allows the use of the etching process without using an etching mask.

As the thickness of wafers has become very thin, from 100 μm to 50 μm, and then to 30 μm, the dicing method for separating it into individual chips is also changing from breaking, blading, and laser to plasma. With the sophistication of the dicing method, the production cost of dicing itself increases, but dicing defects frequently found in semiconductor chips such as chipping and cracking have significantly decreased. Also, due to the increased number of chips on the same wafer, the production cost per chip decreases. The increase in the number of chips per unit area is related to the narrowing of the dicing street width (kerf width) within the scribe line, along with the evolution of the dicing method. The number of chips on a wafer where plasma dicing is applied can be increased by nearly 20% compared to blade dicing. Because of this economic effect, the plasma method is preferred. In addition to wafer processing technology, various dicing process methods such as DBG are emerging according to the external changes of wafers and chips, and the package method.

The post Singulation, the Moment When a Wafer is Separated into Multiple Semiconductor Chips first appeared on SK hynix Newsroom.